The Universal Verification Methodology UVM has compelling advantages for IC verification but can be challenging to adopt, according to panelists from four user companies at an Accellera breakfast at the recent Design Automation Conference DAC 2014.  Panelists discussed reasons for moving to UVM, costs of adoption, whats still needed, whether the current feature set should be “frozen,” and the need for a multi-language UVM standard.The panel was moderated by John Aynsley, CTO of training firm Doulos far left in photo. Panelists were as follows, shown left to right in the photo below.Mohamed Elmalaki, IntelRich Newton, EricssonColin McKellar, ImaginationAmol Bhinge, Freescale

via Accellera DAC 2014 Breakfast—What Engineers Really Think About UVM – Industry Insights – Cadence Community.