Webinar Thursday June 26, 2014

Aldec (www.aldec.com) is hosting a Webinar on OSVVM – Open Source VHDL Verification Methodology on Thursday June 26, 2014. 

Europe/India session: Enroll with Aldec

OSVVM provides functional coverage and randomization utilities that layer on top of your transaction level modeling (tlm) based VHDL testbench. Using these you can create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests. This simplified approach allows you to utilize advanced randomization techniques when you need them and easily mix advanced randomization techniques with directed, algorithmic, and file-based test generation techniques. Best of all, OSVVM is free, works in all of Aldec and some other VHDL simulators.

Europe Session 3-4 pm CEST 6-7 am PDT 9-10 am EDT Enroll with Aldec

US Session 11 am-12 Noon PDT 2-3 pm EDT 8-9 pm CEST Enroll with Aldec

via OSVVM™ Webinar  | Open Source VHDL Verification Methodology.