Formal analysis provides exhaustive results for any problem its applied to, so wouldnt it be great if the many uncertainties around the completeness of verification could eventually be eliminated with this powerful technology? In this post I cite examples of customers who are taking big steps in this direction by using formal to completely replace simulation for many block, unit, and even system-level verification applications.
▶ Formal Will Dominate Verification — Heres Why, from Joe Hupcey III
Web event: VCS AMS for Advanced SoC Mixed-signal Verification Date: September 3, 2014 Time:10:00 AM PDT The growth in mixed-signal SoC designs is driven by many factors, including cost, perfo...Read more
CVC releases free resource – SystemVerilog interfaces, step-by-step guide » GO 2 UVM – for VLSI Designers
CVC along with Aldec releases a recorded webinar on SystemVerilog Interface. Making your first step into UVM? You absolutely need to create a SystemVerilog interface so that your UVM testbench can ta...Read more