Formal analysis provides exhaustive results for any problem its applied to, so wouldnt it be great if the many uncertainties around the completeness of verification could eventually be eliminated with this powerful technology? In this post I cite examples of customers who are taking big steps in this direction by using formal to completely replace simulation for many block, unit, and even system-level verification applications.

via ▶ Formal Will Dominate Verification — Heres Why – YouTube.