CVC along with Aldec releases a recorded webinar on SystemVerilog Interface.

Making your first step into UVM? You absolutely need to create a SystemVerilog interface so that your UVM testbench can talk to your DUT. Want to learn how to do it step-by-step? Learn from this 1 hour webinar archive delivered by Srinivasan Venkataramanan, Chief Technology Officer @CVC along with Aldec

via Free resource – SystemVerilog interfaces, step-by-step guide » GO 2 UVM – for VLSI Designers.