Go2UVM.org, the premier UVM learning site has published a handy quick start guide to UVM register modelling for standard IPs. It also promises to make available to users a series of UVM Register models for popular IPs based on OpenCores shortly.
Go2UVM publishes a smarter, faster way to UVM register model creation
CVC releases free resource – SystemVerilog interfaces, step-by-step guide » GO 2 UVM – for VLSI Designers
CVC along with Aldec releases a recorded webinar on SystemVerilog Interface. Making your first step into UVM? You absolutely need to create a SystemVerilog interface so that your UVM testbench can ta...Read more
Functional verification is becoming a bottleneck and is affecting all design teams. It’s in a chip’s best interest that you as a design engineer make an effort to boost verification productivity. ...Read more