Attendees Will Learn:
- Dynamic part selection; no need for re-compilation when selecting new part
- Intelligent, built-in JEDEC compliant Protocol and timing checks
- Pre-defined CoverGroups for Memory State transition, training and power down modes, and more
- Direct testbench access to the Memory Core for peek, poke, and set/get/clear any memory location attributes
- Error injections into transactions
- Synchronized debug between transactions and signals
via TechOnline Webinar.