Are you a die-hard Verification fan? Are you looking to improve on your UVM skills in a real “bug hunting” event?VerifLabs,, a new venture from CVC is pleased to announce “SystemVerilog-UVM, Verification Hackathon”. As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going with the industry’s most popular, advanced Functional Verification framework – UVM.When: 22-Nov-2014, Saturday,10.00 AM onwards till evening @ CVC, BengaluruRegister at:

via SystemVerilog-UVM, Verification “Hackathon” » GO 2 UVM – for VLSI Designers.