Agnisys Webinar: The Complete Solution for Register Specification, Design and Verification
When: Wednesday, November 12, 1:00 to 2:00 PM Eastern Standard Time
Who should attend: Spec Writers, Architects, Designers, Verification Engineers, Firmware Developers
What will you see:
- How to develop correct-by-construction register definitions from a single register specification
- Auto-generation of a range of outputs from a single specification
- Accepting Word, Excel, SystemRDL, XML, IP-XACT, CSV, Framemaker, RALF, and custom inputs
- Generating Verilog, VHDL or SV RTL, UVM, C/C++ Headers, RAL, XML, IP-XACT, SystemRDL, custom outputs (via Tcl), PDF, HTML
- Support for all popular bus types like AXI, AHB, APB, AVALON etc.
Advanced topics such as:
- multiple bus domains,
- backdoor access,
- low-power RTL and
- special registers
- Auto generation of the “Complete” verification environment, over and above UVM including bus agents, virtual sequencers, RTL, associated tests, and an annotated verification plan
To reserve your spot in the Webinar, please register now!