The Verification Spectrum

Typically, verification teams develop separate flows to support verification at block and SoC levels. As well as supporting reuse between these different abstraction levels, the verification environment should be reusable at different stages of the verification process, to minimize effort.

 

Figure 1: Two dimensions of the verification spectrum

via SystemVerilog Test Suites Accelerate IP-to-SoC Reuse | VIP Central.