VerifLabs, a new venture under CVC is proud to announce a workshop on SystemVerilog constraints. This is a DIY – Do-It Yourself style workshop and NOT a training! You need to know the lingo, construct and have verification background to “Do-It”.
Date: Jan 31, 2015
Time: 10 AM – 5 PM (walkin anytime, will allow 2-3 hours per candidate)
Venue: CVC Premises, Bangalore, India, see: http://cvcblr.com/?page_id=2
See more at: http://veriflabs.com/2015/01/free-systemverilog-constraint-workshop/
Sponsored Tutorial at DVCon 2015 Thursday, March 4 8:30am - 12:00pm
Verification 501: Graduate-level Debug Tutorial
Welcome returning students! In last year’s “Revolutionary Debug Techniques...
Release 9.0 of the Blue Pearl Software Suite decreases development time with the new Debug Environment by shrinking the time to find and correct design mistakes.
Key features include: