One of the long standing independent EDA companies, Real Intent has significant updates at this year DVCon US. Our VerifNews team caught up with Graham Bell, Vice President of Marketing at Real Intent at their booth at the event. Here is a transcript:

 

VN: Tell us about your company please

GB: Real Intent is a Verification EDA company founded in 1999 by Prakash Narain & Rajiv Kumar. They both had extensive Design & Design flow experience at companies like SUN, HP and others. They produced a formal verification product around ABV (Assertion Based Verification). Around 2008 they refocused and created solutions for CDC (Clock Domain Crossing), SDC constraints management, X-propagation and RTL Linting.

VN: How long have you been exhibiting at DVCon?

GB: From its inception really! Starting with the days of HDLCon (The earlier name for this conference, see a long history at: http://verifnews.org/dvcon-india-2014/history-of-dvcon-dvcon-india/ ).

VN: How do you see customer enthusiasm relative to previous years?

GB: Every year the customer enthusiasm has been growing with thoughts like, how do we do clean design, Design for Verification, in other words “Verification aware Designs“. Also conversations around SoC scenario modelling, verification of such scenarios etc. There is good amount of discussion on what do we ship along with IPs and SoC to our end customers.

VN: Would you be exhibiting at DVCon India 2015?

GB: Oh sure, we did so in the inaugural edition in 2014 and are hoping to continue this year as well! We also promoted that event to our customers and design community. VN team adds: Real Intent also provided highly qualified technical support during the DVCon India 2014 Technical Review Process be donating some of our time through Lisa Piper, Technical Marketing Manager, Real Intent. We hope to continue that contribution in 2015 as well

VN: What are your new additions, offerings this year?

GB: We just announced our new release of Ascent Lint product with DO-254 support. We also added 17 new VHDL rules, several Verilog rules and some SystemVerilog rules as well. Ascent also does deeper FSM analysis for VHDL designs now.

RI_booth

 

VN: Thanks Graham for the time and insights, appreciate it. See you later at DVCon India.