As part of our continued and relentless news coverage of major Design Verification news across the globe, we at VerifNews covered the recent DVCon USA 2015 via a combination of questionnaire, photos and audio recordings. Here is what our team learnt about Synopsys’s major push in the Verification space. We sincerely thank Michael Sanie, Senior Director, Verification Marketing at Synopsys for sharing his thoughts with our VerifNews team at DVCon US.
Q: How long have you been at DVCon?
A: “As long as it existed” – that’s “continuum” indeed!
Q: How do you see customers enthusiasm around DVCon?
A: Energy is lot more and has been consistently growing. The level of discussions, booth visits has been growing. Its one of the best shows for the Design-Verification space around the world!
Q: Share with us the exciting news around Synopsys Verification offerings
A: Since the launch of Verification Compiler back in DVCon 2014, we have been constantly adding technologies into it and integrating more emulation, VIPs etc.
Inline with this thought was the keynote by Aart J. De Geus, CEO of Synopsys.
The major shift according to Synopsys is the way the chip design companies, especially those working on SoCs with a large software content are thinking about early verification start of both hardware and software.
The following pictures sort of summarize the shift.
The crux of the message/vision being, bring the hardware and software development to be in parallel and run them in “lock-step” mode than the traditional “one-after-the-other” approach.
Aart went on to say “This may sound like a dream”, but as part of our enhanced focus around “Verification Continuum” we are bringing multitude of technologies, tools, models and VIPs to make this a reality.
And to make that picture more alive, here is our capture of Synopsys booth at DVCon USA 2015.
Below is a link to the full length audio interview of Michael Sanie at DVCon US. Enjoy the audio, especially the last part where envisions DVCon in China soon!