Our VerifNews team spoke to Michael Ligthart (ML) President of Verific Design Automation at their booth at DVCon USA 2015. Our parent company CVC (http://www.cvcblr.com) covered Verific before at DAC 2013 at Austin, the older news buzz can be found at: http://cvcblr.com/?p=767
VN: How many years you’ve been exhibiting at DVCon?
ML: We have been here for about 4-5 years.
How do you see customers enthusiasm around DVCon?
VN: We build SV & VHDL parser. We also introduced UPF parser. It fits nicely into our strategy
ML: Consistent over last few years. I used to attend this event in 2008 as an attendee and back then the audience were quite small. Since 2009 there has been good upswing. Hence decided to exhibit in next years. Over last few years it has been around 700-800 and consistent.
VN: What are your key products/news around this DVCon?
ML: We build Verilog, SystemVerilog & VHDL parsers and not end user level EDA tools. In that sense we are different kind of an exhibitor. Our main customers are the EDA companies around us here, FPGA companies and major semiconductor companies. This year we have introduced a new IEEE 1801 UPF parser and enhanced SV support for 2012.
VN: What would be your focus for the upcoming quarters?
ML: Improving quality and increasing customer base will be the main focus. Potentially we could add some of the new, upcoming SV 2016 features, but that depends on how many new features get added by the IEEE committee.
VN: Will you be exhibiting at DVCon-India 2015?
ML: I don’t know yet for sure. But we are considering it. Our team in Kolkata, India would make that call later this year
VN: Thanks and best wishes!