Over the last half-a-decade, FPGAs have been becoming larger and larger in capacity and narrow/deep in technology nodes.  Given the cost advantages of FPGA, various companies that were erstwhile ASIC-only design houses have taken FPGA as the first step to production and/or prototyping. . As learnt in the ASIC domain, as designers’ ability to push more logic into a single chip grows, the verification of the functionality, timing and related aspects start exploding.

Just like the way the HDL synthesis requires specific tweak cross ASIC vs. FPGA, the verification also requires tweaks,  solutions to target FPGA verification. This has been the focus of Blue Pearl Software Inc (BPS)

Recently our VerifNews (VN) team caught up with Shakeel Jeeawoody, Vice President, Marketing at Blue Pearl Software (BPS)  at their DVCon USA 2015 booth for a quick chat. Below is an excerpt:

VN: How many years have you been exhibiting at DVCon?

BPS: We have been here for the last 3 to 4 years and we see lot of value and that’s why we keep coming back.

VN: How do you see customers enthusiasm around DVCon? Any thoughts on how you see the change over the last few years?

BPS: Couple of years ago, Verification was just on the radar screen of many attendees here, but now it has become must for each one of them. It has also evolved from just functional verification to VIPs, formal and more recently FPGA prototyping.

 

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VN: What are your key products/news around this DVCon?

BPS: One of the latest things we are announcing is “Design Debugging”. So far our focus has been on RTL analysis and verification. We have been hearing that users are spending more time in debugging the results of these analysis and time to go and fix their RTL. That’s why we have taken the first step into providing an integrated environment to analyze and fix the RTL quickly.

VN:Will you be exhibiting at DVCon-India 2015?

BPS: We haven’t decided yet, we will decide in the second half of this year. For now we are exhibiting at Embedded World Conf, DVCon USA, SNUG USA,DAC etc.

VNAny other news that you want to share with our VerifNews.org readers?

BPS: Our company focuses on FPGA. We believe we have a very strong solution in this space and have been doing so for last 4-5 years. We have an advanced CDC visualization environment called ACE  (http://verifworks.com/an-ace-visualizer-for-your-designs-clocking-structure-welcome-to-bluepearls-ace/). We also provide a novel approach to model IPs that are treated as Blackboxes to enable deeper, comprehensive CDC at chip level. We call this as User Grey Cell Methodology. I suggest VerifNews readers to try this out.

VN: Thanks so much Shakeel for talking to us and good luck!