Around the industry’s most popular event, there is a BIG news for the VLSI/ASIC Design & Verification industry: Synopsys buys Atrenta:
As part of Synopsys’s new initiative to deliver a “Verification Continuum” (as reported by our VerifNews team at recent DVCon USA 2015, http://verifnews.org/2015/03/synopsys-sees-a-major-shift-left-approach-to-verification-at-dvcon-us-2015/) this is a very strong, bold and useful step for its customers. Since Atrenta’s leading solutions in SoC RTL Design Verification such as SpyGlass and GenSys are widely used by many customers across the globe, this would fill the apparent gaps in Synopsys’s RTL Static Verification Space.
What would also be very valuable to the industry at large is the availability of Assertion Synthesis technology through BugScope (An EDA tool that came into Atrenta through its NextOp acquisition a while back). In a nut-shell this tool extracts high quality “design properties” from a running simulation setup, see: http://www.cvcblr.com/blog/?p=147 and http://www.cvcblr.com/blog/?p=163 for quick introduction.
This is interesting particularly b’cos it strengthens Synopsys’s abilities to penetrate the Formal Verification (FV, Model Checking) market more aggressively. It should also expand Synopsys’s not-so-old acquisition of EVE ZebU emulation platform by allowing users to explore ABV in Emulation. Though this could take a while to marry these different technologies, Synopsys has the muscle power and the vision to deliver on this continuum. This should be very exciting times for those work in DV field!