This is a continuum on my recent discussion with Harry Foster from Mentor Graphics at a recent “Verification Seminar” in Bangalore (Part-1: http://verifnews.org/2015/07/dvcon-harry-foster-the-dvcon-india-2015-countdown-70-days-to-go/)
[VN] How would you like to see DVCon India shaping up?
[HF] First and foremost is the quality. Given the local talent pool I’m quite sure it will be very high. While the user papers are the bulk of the conference, we should explore adding discussion panels. Duration can be extended from current 2 days to accommodate wide spread interest like we do at DVCon US.
[VN] Harry, what are your forecasts for our industry?
[HF] We at Mentor Graphics conduct a professional, detailed survey through a well-recognized agency, Wilson Research Group. Our latest survey was done in 2014 and I have been blogging about the findings at: http://bit.ly/1Ifx6yA
In this 2014 edition of this survey, unlike my previous Wilson Research Group functional verification study blogs, which focused on the ASIC/IC market, I began with an exclusive focus on FPGA trends. While your readers can find detailed results, findings at the blog site mentioned above, a quick summary would be:
- According to the survey this it will be positive growth like last two years globally.
- FPGA market is really picking up very well for advanced verification. And the FPGA field is no longer VHDL dominant one, Verilog and SystemVerilog is also present and growing.
[VN] How can I miss to discuss assertions with Harry Foster, the unofficial Godfather of ABV (Assertion Based Verification)?
[HF] Of-course it is well beyond statistics that many in the industry agree assertions are effective. However I see ABV not adopted well enough. I believe that the process and practices of assertions are not given its due importance so that could be a reason for its lesser reachability. Debugging is at times painful in ABV. Some argue that Time To Market (TTM) pressure alienates Assertion usage, though in reality ABV finds bugs earlier and closer to the source. In Assertions, the syntax is fairly simple, makes it interesting. However the methodology and the mindset is key issue here.
[VN] Does Automatic assertions or the “Assertion Synthesis” help here?
[HF] There are solutions in this space like Nextop, Propgen (From Mentor’s Questa). However prioritization of bugs found and phase of the project is the key. Clearly there is a lack of Methodology here.
[VN] It was pleasure speaking with you face to face Mr. harry Foster. Given that you will be speaking at DVCon India 2015, we look forward to hosting you here at DVCon India!
The DVCon India countdown: