IEEE, the world’s largest professional association for the advancement of technology is into action that directly impacts (in a positive way) all the Design-Verification community across the globe. In-line with IEEE’s constant endeavours to advancing the technology, it is now accepting a donation from Accellera, an electronics industry standards committee on UVM (Universal Verification Methodology) to make it an IEEE standard in the near future.

As many in this field of VLSI Design Verification would recall, Verification occupied the front row of ASIC & FPGA designs for well over a decade-and-half by now. It all started with HVLs like e (IEEE 1647), OpenVera and these concepts got merged into Verilog (IEEE 1364) and got to SystemVerilog (IEEE 1800). Each of these languages took its own route to IEEE standardization process, however the adoption of these became very wide once the IEEE ratification was done. Below is a brief summary of the history of various HDLs (Hardware Design Languages) and HVLs (Hardware Verification Languages) that have made center stage over the years. IEEE_HDL_HVLs

Summary of various HDLs and HVLs in the VLSI domain and their IEEE references

Once the IEEE 1800-2005 was standardized, the industry started adopting it rapidly. A survey done by Mentor Graphics show this trend clearly:

As more and more design team started adopting IEE 1800 SystemVerilog, a strong need for a methodology around the language was felt. With innovating at the forefront, several methodologies started rolling out, a partial timeline of the various methodologies is below:

VMM_OVM_UVM

Now with UVM being an Accellera standard has reached a certain level of maturity and is now being transferred to IEEE for further proliferation etc.

IEEE has called for the first meeting of this new working group on Aug 6th, please register here to attend via conference call. The call is from 21.30 to 23.30 India time (9am – 11am Pacific Time, US)

So do register, attend and contribute to this growing standard!