Riding on the success of initial few editions of VerifNews’ DVTalk event, we are glad to expand it to Hyderabad, Telangana, India this time. As usual with our start-up mode, finer details are still emerging. We have exciting topics and speakers lined up. Here is a draft agenda for your eyes only! Contact us via verifnews [dot] cvc [at] gmail [dot] com if you need more details.

Registration: Click here to register for DVTalk Hyd

Date: 29-Oct 2015

Time: 14.00 – 19.00 (2.00 PM onwards)

Venue:

Level 1, Midtown, Road no.1, Banjara Hills, Hyderabad

DVTalk Hyderabad Venue

 

Updated Agenda:

14.00 – 14.30: Registration

14.30 – 14.45: Welcome, introduction to DVTalk, Guru Kinagi, VerifLabs, a CVC venture

14.45 – 15.15: Invited Keynote, 5G Roadmap for semiconductor segment, Madhavendra (Shaan) Bhatnagar, Director of  Silicon Engineering  – Microsemi India

15.15 – 15.45: Capturing design requirements using SystemVerilog Assertions (SVA), Raja Bandi, LucidVLSI

15.45 – 16.15: Graph Based Verification of PCIe device, Sundarajan Haran, Microsemi

16.15 – 16.30: Tea Break

16.30 – 17.00: MIPI Verification IP, Nitin Agarwal, Senior Application Engineering Manager, Verification Group at Synopsys Hyderabad

17.00 – 17.30: Vlang – Next generation Verification language, Puneet, Coverify

17.30 – 18.00: Invited keynote on FPGA Verification, Narayana Pidugu, Xilinx Hyderabad

18.00 – 18.30:Qualitative assessment of user’s UVM code base, Srinivasan Venkataramanan, VerifWorks, a CVC venture

18.30 – 19.00: Closing remarks, next event planning