Aldec, Inc., an industry-leading Electronic Design Automation (EDA) company is glad to host a technical seminar on “Hardware-Assisted Verification” in Bangalore, India on Sep 08, 2016. The full-day event has multiple high-profile speakers from the industry and academia:

Aldec_logo cvc_logo IISc_logo

More details and registration link can be found at:

It is FREE of cost, but registration is mandatory and Aldec would like to reserve the confirmation through their local channel partner.


9:00AM-9:30AM      Registration

9:30AM-10:00AM    Introduction to Hardware Assisted Verification

10:00AM-11:00AM  Accelerating the Verification of Hardware Dependent Software

11:00AM-11:15AM  Tea Break

11:15AM-11:45AM  Case Study with IISc

11:45AM-12:45PM  Accelerating UVM based testbenches with Emulation, CVC

12:45PM-1:45PM    Lunch Break

1:45PM-2:30PM      FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms

2:30PM-3:00PM      Accelerating Vivado Designs

3:00PM-3:15PM      Tea Break

3:15PM-4:00PM      Convergence of Prototyping and Emulation

4:00PM-4:15 PM     Conclusions