Aldec, Inc., an industry-leading Electronic Design Automation (EDA) company recently hosted a technical seminar on “Hardware-Assisted Verification” in Bangalore, India on Sep 08, 2016. The full-day event had multiple high-profile speakers from the industry and academia:

Aldec_logo cvc_logo IISc_logo

Below is a brief summary of the day’s proceedings as captured by our team member!

Introduction to Hardware Assisted Verification – Louie De Luna

Louie Director of Marketing at Aldec Inc. USA introduced ALDEC products and tools. He focused on the importance of Hardware assisted verification. Louie introduced various Hardware-Assisted approaches such as simulation acceleration, transaction-level co-emulation, and prototyping.

Accelerating the Verification of Hardware Dependent Software – Chris Szczur

Chris Szczur, Hardware Technical Support Manager at Aldec Poland explained more on the FPGA based emulation and why FPGAs are chosen as the verification platform for software integration. Chris also provided a brief introduction on SCE-MI and the macro based use model to begin with (He followed it later in the day with pipe based use model, see below):

Case Study with ReneLife/IISc – Shanti

Presented on ReneLife Accurate genome signature towards a healthier LIFE!
Explained on human Genome analysis and how they are using Aldec HES as an execution platform to perform billions of computations and analysis. Some of the results shown are very encouraging indeed!

ReneLife_Aldec_HES

Accelerating UVM based testbenches with Emulation – Srini

Starting with standard UVM, Srini @CVC showed how one could move to emulation and gain performance in steps. Beginning with basic UVM skeleton that can be automatically generated using open-source Go2UVM app (www.go2uvm.org) Srini showed the value of standards such as UVM, and the open-source “apps” that go along with UVM to get first-time users quickly started with UVM. He then explained the role of SCE-MI standard with examples in emulation with UVM. He summarized saying migrating a UVM bench to emulation is not hard, well defined standards UVM, SCE-MI, SV-Connect, SV-DPI all help!

UVM_Emu_Summary_Srini

Then Chris took over again to walk audience through topics of

FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms and Convergence of Prototyping and Emulation

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The event was very well co-ordinated by Shivakumar and other AEs of Aldec, India team.