Our next episode of DVTalk is here! Welcome to DVTalk April-2018. In this episode we are thrilled to partner with leading VLSI & EDA companies and standard committee to bring you the latest in this field.
It is free to attend, but registration is mandatory. As seats gets filled quickly, we suggest you register right-away by clicking here: https://tinyurl.com/ieee-uvm
In this edition of DVTalk we have the following organisations have signed up to contribute:
We are excited to have one of the leading developers of IEEE UVM, Mr. Srivatsa Vasudevan as presenter of this “straight from the oven” update! Sri will also be happy to offer his best selling book on UVM titled “Practical UVM” for a nominal cost of Rs. 1500/- during the event, so grab your author signed copies by signing up here via: DVTalk 2018 Registration Link
This event is also intended for budding engineers who look forward to making a flying career in the field of VLSI. In the post-lunch session we have presentations, webinars and demos tailored to fresh engineering graduates keen to know what’s in it for them and a proven route to success with CVC – the global leader in VLSI training. Come and learn for a whole day what “Design Verification Engineering (DVE)” is all about!
9.00 – 9.30 – Welcome, registration
9.30 – 10.00 – Introduction, Agenda
10.00 – 10.45 – UVM for RTL Designers
10.45 – 11.00 – Tea and snacks break
11.00 – 13.00 – IEEE 1800.2 UVM – What’s new? – Straight from the horse’s mouth!
13.00 – 14.00 – Lunch Break
14.00 – 15.00 – VLSI career – introduction and opportunities
15.00 – 16.00 – SystemVerilog Assertions – practical applications
Register here for free: https://tinyurl.com/ieee-uvm