To all our readers, sorry for the silence over last few quarters. Our content writers had moved on and our funding team got busy with other projects. So here we are at a crucial period of time in this world of Design-Verification. With new standards in the making Accellera Systems Initiative, this industry’s premier standards organization  is busy in bringing several new standards.

A brief look at some of these initiatives:


  • UVM – IEEE 1800.2 – UVM, the undisputedly most adopted methodology in electronics design verification field is well poised to release its first IEEE version that can be tested and adopted by early-users late April 2018. Staring with UVM 1.0-EA release, Accellera has constantly upgraded UVM to 1.1 (b/c/d) and UVM 1.2 as the most recent version of UVM from Accellera. CVC, a global leader in VLSI training based in Bangalore, India did a successful “UVM 1.2 Day event” back in 2014. Since then UVM has seen a widespread adoption across the globe and reaching as far as Brazil during Aug 2017 at “Chip-on-the-sands” event. Riding on its phenomenal success, the UVM committee has been working very hard over the last few years to upgrade UVM 1.2 to become an IEEE 1800.2 UVM version. You should be tuned in here to learn more on this development!
  • Portable Stimulus Standard – After the SystemVerilog & UVM standards, industry has been looking to solve modern challenges of software driven test generation. While early days of proprietary standards and solutions existed in this space for a long time, there has been no standard yet! Accellera PSS attempts to fill this void. The standard has been available as an early-beta for user feedback and is slated to become 1.0 standard very soon. Learn more at:
  • IP Security Assurance Specification – Accellera has proposed the formation of a new working group to focus on defining security assurance requirements for IP. Its first meeting is scheduled for late April 2018. More details at:
  • IP-XACT   – Industry is gearing up for new feature requests in this popular IEEE standard to tackle recent advances in electronic system design.
  • SystemC, AMS etc.


And with major EDA vendors starting to implement these upcoming standards, the world of VLSI Design-Verification is experiencing exciting times indeed!

Signing-off with a desire to come back shortly,

Your friendly VerifNews reporter 🙂