VLSI Design-Verification as a field is booming over the last decade. More so with the advent of UVM (Universal Verification Methodology) as a standard from Accellera back in early 2000-s. UVM has grown leaps and bounds and has been adopted by almost every ASIC design team across the globe. Growth of industries like IoT, automobile electronics fuelled more engineers doing electronic design than every before. In any industry, adoption of a standard depends certain key factors such as:
- Easy accessibility to collaterals
- Simplified use-models, examples
- Knowledge dissemination of key aspects of the standard
The early days of UVM targeted advanced engineers with deep object-oriented expertise. Technically that’s the key reason why UVM has been a great success. However for a standard to be adopted by wider user-base, it needs to be made simple to begin with, and ideally free for first-timer users.
CVC (www.cvcblr.com), a name that’s so synonymous to advanced verification since early 2000 across the globe, has been at the center of deploying SystemVerilog through its various training modules, papers at popular events across the globe such as DVCon USA, DVCon Europe, India and DAC in the USA. Led by IIT-ians Mrs. Ajeetha and Srini, CVC has become a Global Leader in VLSI training through their popular UVM courses delivered at various parts of the globe. Recently CVC has teamed up with VerifWorks, a high-end DV consulting company to release a FREE eBook on UVM. Through this book the authors share their deep knowledge in this domain with first-time UVM users without having to wait for a formal training. Of-course a natural progression would be to take up a formal training once the readers are familiar with the basic concepts provided in this free eBook.
As part of its UnleashingUVM story, CVC delivers various workshops on UVM and other VLSI topics across India, typically for Universities and Engineering colleges. Universities can sign-up for a free workshop via www.cvcblr.com