Posts by CVC Bangalore (cvcblr)

Jul
01
2014

Cadence and ARM Expand Collaboration for 64-bit Processor Designs

SAN JOSE, Calif., 20 May 2014 Highlights: EDA Technology Access Agreement gives Cadence access to ARMv7 and ARMv8-A architecture-based processor IP, ARM® Mali™ GPUs, System IP and physical libraries to enable tools optimized for these IPs and the development of designs achieving the required power, performance and area (PPA) First such agreement for ARM’s 64-bit […]

Jun
26
2014

DO-254/CTS™ solves Elbit’s major challenges – Blog – Aldec

Aldec has been working closely with Elbit Systems in Israel on an important DO-254 project for some time now. Using Aldec’s specialized solution DO-254/CTS™ as their primary FPGA physical testing platform, Elbit recently passed a critical EASA verification audit for DO-254/ED-80 DAL A FPGAs. via DO-254/CTS™ solves Elbit’s major challenges – Blog – Aldec.

Jun
25
2014

UVM 1.2 is officially released – June 24th 2014

After successful tests and trials at several companies, official UVM 1.2 release is now publicly available for one and all! Download UVM 1.2 Tar Ball Accellera Systems Initiative released UVM 1.2 today, June 24, 2014. It’s available for immediate download. There is also a new forum open on the Accellera site to collect your feedback and […]

Jun
23
2014

Why DVCon India is so exciting? – Views from various stakeholders, part-1

In case you haven’t heard the BIG news for 2014 in VLSI Design field in India, here you go: DVCon, the most popular Verification centric conferences across the world in the field of Electronics (VLSI) Design is expanding to other geographies in 2014. After successful run in the USA for well over the last decade, […]

Jun
21
2014

VHDL Testbench techniques: OSVVM™ Webinar Thursday June 26, 2014 | Open Source VHDL Verification Methodology

Webinar Thursday June 26, 2014 Aldec (www.aldec.com) is hosting a Webinar on OSVVM – Open Source VHDL Verification Methodology on Thursday June 26, 2014.  Europe/India session: Enroll with Aldec OSVVM provides functional coverage and randomization utilities that layer on top of your transaction level modeling (tlm) based VHDL testbench. Using these you can create either basic Constrained […]

Jun
20
2014

Cadence Completes Acquisition of Jasper Design Automation

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has completed the acquisition of Jasper Design Automation, Inc., a market and technology leader in the fast-growing formal analysis sector. The completion of this transaction expands differentiation of Cadence’s System Development Suite, the industry’s first and broadest system […]

Jun
18
2014

Accellera DAC 2014 Breakfast—What Engineers Really Think About UVM – Industry Insights – Cadence Community

The Universal Verification Methodology UVM has compelling advantages for IC verification but can be challenging to adopt, according to panelists from four user companies at an Accellera breakfast at the recent Design Automation Conference DAC 2014.  Panelists discussed reasons for moving to UVM, costs of adoption, whats still needed, whether the current feature set should […]

Jun
12
2014

DVCon India 2014 – Call for Abstracts

The Design and Verification Conference & Exhibition India DVCon India is a new technical conference in India targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon India is similar to the successful DVCon United States […]

Jun
07
2014

Yatin Trivedi receives 2014 Leadership Award -fromAccellera Systems Initiative

Yatin Trivedi will receive the 2014 Accellera Leadership Award in recognition of his leadership, organizational and financial vision, and service to the standards industry.   via Yatin Trivedi 2014 Leadership Award – Accellera Systems Initiative.

Jun
06
2014

Universal Verification Methodology IDE Available NowAgnisys

Agnisys Offers DVInsight – A System Verilog – Universal Verification Methodology IDE San Francisco, CA. June 2nd, 2014 – Agnisys, Inc. Launches DVinsight™, an Integrated Development Environment (IDE) for creating System Verilog (SV) test bench code for semiconductor verification projects that conform to the Universal Verification Methodology (UVM) guidelines. via Universal Verification Methodology IDE Available NowAgnisys.


//www.


© 2014 Verifnews All rights reserved.
Designed By SCSVMV University