Posts by CVC Bangalore (cvcblr)

Jun
05
2014

Avery Revs PCIe and eMMC Verification IPs HMC, LRDIMM, Soundwire… – Avery Design Systems

ANDOVER, MA., May 28, 2014 – Avery Design Systems Inc., a leader in verification IP, today announced availability of a major new release of the flagship PCIe VIP, major VIP update for eMMC 5.X, and new VIP introductions for HMC, LRDIMM, Soundwire, UHS-II, and CAN FD.  The Avery VIP portfolio is now 100% implemented in […]

Jun
05
2014

SpyGlass By Atrenta : Industry News and Atrenta News

SAN JOSE, Calif. – May 30, 2014 – Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, will showcase the next generation of RTL Signoff solutions at the  51st Design Automation Conference (DAC) to be held June 1-5, 2014 at the Moscone Convention Center in San Francisco, CA.  […]

Jun
05
2014

Avery Targets Low Power Retention Register Synthesis – Avery Design Systems

ANDOVER, MA., May 28, 2014 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today introduced a new low power design optimization solution, RetentSYN, targeting area and leakage power reduction in low power designs.  RetentSYN’s patent pending solution automatically identifies registers that do not require retention during power-down cycles and generates optimized […]

Jun
05
2014

▶ Whiteboard Wednesdays – Accelerated Verification IP to Improve Hardware Verification – YouTube

In this week’s Whiteboard Wednesdays, Tom Hackett talks about Accelerated Verification IP (VIP) and how it makes hardware verification more efficient and productive. via ▶ Whiteboard Wednesdays – Accelerated Verification IP to Improve Hardware Verification – YouTube.

Jun
04
2014

SmartDV Opens US Office, Demonstrates Verification IP Portfolio at 2014 Design Automation Conference | Business Wire

Design Automation Conference 2014 SAN FRANCISCO–(BUSINESS WIRE)–DAC – SmartDV, the verification intellectual property (VIP) company, is demonstrating its portfolio of high quality standard and custom protocol VIPs at the Design Automation Conference (DAC) this year for the first time. The company opened a US office in San Diego to meet growing demand for its portfolio […]

Jun
04
2014

Breker Verification Systems Becomes Synopsys VIA Access Program Member – Yahoo Finance

Breker Verification Systems Becomes Synopsys VIA Access Program Member via Breker Verification Systems Becomes Synopsys VIA Access Program Member – Yahoo Finance.

Jun
04
2014

IP Accelerated Initiative

IP Accelerated Initiative via The Eyes Have It » Blog Archive » IP Accelerated Initiative.

Jun
04
2014

Whiteboard Wednesdays – Improving Hardware Verification with Accelerated Verification IP (VIP) – Whiteboard Wednesdays – Cadence Community

Improving Hardware Verification with Accelerated Verification IP (VIP) via Whiteboard Wednesdays – Improving Hardware Verification with Accelerated Verification IP (VIP) – Whiteboard Wednesdays – Cadence Community.

Jun
03
2014

VTRAN Vector Translation Tool | Chip Design

VTRAN Vector Translation Tool With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors. Whether you need to translate VCD or EVCD simulation dump files into a test program for one of the popular device testers, or you are […]

Jun
03
2014

Blue Pearl Software Announces Release 8.1 with Advanced Clock Analysis

Santa Clara, California – May 27, 2014 – Blue Pearl Software, Inc., the provider of EDA software that accelerates IP and FPGA verification, announces release 8.1 of its software suite for Windows® and Linux® operating systems. It introduces Advanced Clock Analysis that allows designers to visually verify and get guidance on their clock domain crossings […]


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