Apr
24
2015

D&R IP-SOC Days – Bangalore, 2015 event

– Bangalore, 2015 : Highlights                      – an EDA portal based out of Europe has been successfully running its “IP-SOC Days” for the past several years across the world. This year the Bangalore edition was held at the Park Plaza, ORR, Bangalore on March 25, 2015. Surprisingly not so well marketed on social media, this […]

Apr
01
2015

FPGA Verification done the smart way – the Bluepearl way!

Over the last half-a-decade, FPGAs have been becoming larger and larger in capacity and narrow/deep in technology nodes.  Given the cost advantages of FPGA, various companies that were erstwhile ASIC-only design houses have taken FPGA as the first step to production and/or prototyping. . As learnt in the ASIC domain, as designers’ ability to push more logic into a single […]

Mar
16
2015

Real Intent adds DO-254 checks, enhances SystemVerilog, VHDL support

One of the long standing independent EDA companies, Real Intent has significant updates at this year DVCon US. Our VerifNews team caught up with Graham Bell, Vice President of Marketing at Real Intent at their booth at the event. Here is a transcript:   VN: Tell us about your company please GB: Real Intent is a Verification […]

Mar
16
2015

Blue Pearl Software Introduces Debug Environment in Release 9.0 – Visual Debug and Verification Dramatically Shortens Design Cycle Time

SANTA CLARA, Calif., Feb. 11, 2015 (GLOBE NEWSWIRE) — via PRWEB – Blue Pearl Software, Inc., the provider of EDA software that accelerates IP and FPGA verification, announces release 9.0 of its software suite for Windows® and Linux® operating systems. It introduces the new Blue Pearl Debug Environment that significantly reduces the time it takes […]

Feb
19
2015

Blue Pearl Software Introduces Visual Debug and Verification in latest Release 9.0

Release 9.0 of the Blue Pearl Software Suite decreases development time with the new Debug Environment by shrinking the time to find and correct design mistakes. Key features include: Access to the HDL database once a design is loaded RTL to schematic cross probe Advanced tracing to specific design elements Hierarchical name search and Net […]

Aug
14
2014

ARM Connected Community – Blue Pearl Software: Suit up to ACE Your Clock …

Earlier this year, designers were telling us that they have a bottleneck in their design flow for CDC analysis. In order to get useful results from a CDC analysis, they need to properly set up clock domains, but it’s hard to figure out what the clock domains should be until they’ve done a CDC analysis. […]

Aug
12
2014

Use Advanced Clock Environment (ACE) FREE for your current CDC Analysis

Blue Pearl Software Use Advanced Clock Environment (ACE) FREE for your current CDC Analysis With Advanced Clock Environment, we load your design and provide a graphical representation of the clocks and clock domains. Since many of you have reported that CDC setup is a bottleneck in your flow, we are providing a free version of […]

Jun
03
2014

Blue Pearl Software Announces Release 8.1 with Advanced Clock Analysis

Santa Clara, California – May 27, 2014 – Blue Pearl Software, Inc., the provider of EDA software that accelerates IP and FPGA verification, announces release 8.1 of its software suite for Windows® and Linux® operating systems. It introduces Advanced Clock Analysis that allows designers to visually verify and get guidance on their clock domain crossings […]


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