Jun
08
2015

Synopsys buys Atrenta, builds on Verification Continuum

Around the industry’s most popular event, there is a BIG news for the VLSI/ASIC Design & Verification industry: Synopsys buys Atrenta:       As part of Synopsys’s new initiative to deliver a “Verification Continuum” (as reported by our VerifNews team at recent DVCon USA 2015, http://verifnews.org/2015/03/synopsys-sees-a-major-shift-left-approach-to-verification-at-dvcon-us-2015/) this is a very strong, bold and useful step for its […]

Jun
02
2015

Invionics 48 Hour DAC Design Challenge

Invionics offers an IC development and design automation rapid development platform for semiconductor companies called Invio™. I’m excited to announce that Invionics will demonstrate the rapid development capabilities of the Invio™ EDA Rapid Development Platform at the Design Automation Conference (DAC) 2015 (booth #2507) with a 48 hour DAC Design Challenge.  Invionics engineers will attempt to create a user suggested front-end […]

Jun
02
2015

Invionics Offers Industry’s First Development Platform for Custom Analog and Mixed-Signal EDA Tools

Invionics Offers Industry’s First Development Platform for Custom Analog and Mixed-Signal EDA Tools Verilog-AMS module extends Invio (TM) platform, enables mixed-signal IC innovation Vancouver, British Columbia, May 19, 2015 – Invionics, a company providing software to automate the semiconductor design and verification process, today expanded the InvioTM Platform with a Verilog-AMS add-on module. The new […]

Jun
01
2015

Defacto to announce new release and share customer experience during DAC 2015

Defacto Technologies is excited to announce new releases of its products and share customer experience during DAC in San Francisco, June 8-10. Defacto team will be showcasing breakthrough RTL “Build&Signoff” EDA solutions with new releases of its STAR RTL and Gate-level Design tools. Please visit us at the booth #1902 for in-depth technical presentations. Send […]


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