Verification Leaders unleash UVM via book, examples and workshops

VLSI Design-Verification as a field is booming over the last decade. More so with the advent of UVM (Universal Verification Methodology) as a standard from Accellera back in early 2000-s. UVM has grown leaps and bounds and has been adopted by almost every ASIC design team across the globe. Growth of industries like IoT, automobile […]


DVTalk – Apr’18: VLSI Career workshop, IEEE UVM and more

Our next episode of DVTalk is here! Welcome to DVTalk April-2018. In this episode we are thrilled to partner with leading VLSI & EDA companies and standard committee to bring you the latest in this field. It is free to attend, but registration is mandatory. As seats gets filled quickly, we suggest you register right-away […]


DVTalk Aug 2016 – VLSI industry & UVM adoption

VerifNews is glad to announce  a new #DVTalk session titled: VLSI industry & UVM adoption Brief agenda: 1.       VLSI industry overview . 2.       UVM apps and open-source approach (Courtesy: 3.       Hidden gems of UVM debug This is an exclusive DVTalk event being held at Amrita Bengaluru Campus. Date: Aug 31st 2016 Time: 10.30-12.30 Stay tuned for event […]


DVTalk on SystemVerilog Assertions & UVM at BMS College, Bangalore

Our next DVTalk event will be held at BMS college of Engineering, Bangalore.  BMS is holding a 3-day hands-on workshop on “Advances in Verification Methodologies” from Jun 13-15 2016. VerifWorks will be delivering a session on SystemVerilog Assertions and Go2UVM traces for assertions. Complete agenda is below:


Amrita Univ hosts VLSI-SATA 2016 conference

Leading academic institution Amrita University is organizing the Second IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA 2016) from 10th – 12th January, 2016. The first edition in 2015 was well attended by various industry leaders from Cadence, CVC, Mentor Graphics, AMD and many others along with academicians, students and practising engineers. Riding on […]


DVTalk Hyd Oct29, agenda

Riding on the success of initial few editions of VerifNews’ DVTalk event, we are glad to expand it to Hyderabad, Telangana, India this time. As usual with our start-up mode, finer details are still emerging. We have exciting topics and speakers lined up. Here is a draft agenda for your eyes only! Contact us via […]


DVTalk Oct-6 agenda

Detailed agenda (close to final) for upcoming DVTalk event is below. It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basis. Please register here:   DVTalk Oct 6th, Tuesday Doubletree Hotel, Outer Ring Road, Sarjpaur Signal, Bangalore Track Time Topic Speaker Organization Women […]


DVTalk – Go2UVM workshop on Sep 20, 2015

VerifNews is organizing another session of DVTalk as part of Phase-Shift 2015 event at BMS college of engineering on Sep 20th, 2015. Through its parent organization, VerifNews has gathered a good set of high quality speakers and a great topic for this exciting event. Some of the technologies that are being covered in this event […]


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