Jun
21
2016

DVCon India 2016 – curtain raiser

Welcome to VerifNews Readers! The clock is ticking: Counting Down To DVCon India We had a great start to DVCon India in 2014. Here is an article we did on the history of DVCon India – History of DVCon, DVCon India That’s wonderful, one-off success, maybe? We had a second time success in DVCon India 2015 – it […]

Jun
13
2016

DVTalk on SystemVerilog Assertions & UVM at BMS College, Bangalore

Our next DVTalk event will be held at BMS college of Engineering, Bangalore.  BMS is holding a 3-day hands-on workshop on “Advances in Verification Methodologies” from Jun 13-15 2016. VerifWorks will be delivering a session on SystemVerilog Assertions and Go2UVM traces for assertions. Complete agenda is below:

Feb
25
2016

DVCon 2016 is next week – preview of our contributions

DVCon 2016 is next week – preview of our contributions The primary annual technical carnival of the VLSI & EDA industry focusing on front-end design is DVCon. Since its inception several years ago (a very good history of DVCon is at: DVCon History), DVCon has spread its wings across the globe with India and EU editions […]

Feb
24
2016

Debug Data API Debut Meeting March 1st 

Message from Adam Sherer, Cadence on Debug-Data API meeting @DVCon US Fittingly, our first working proof of concept will happen on March 1st.  We will have a meeting of Debug Data API interested folks attending DVCon U.S. From 5:15p to 5:45p on Tuesday March 1st in the Fir Ballroom at the DoubleTree Hotel in San […]

Jan
11
2016

Amrita Univ hosts VLSI-SATA 2016 conference

Leading academic institution Amrita University is organizing the Second IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA 2016) from 10th – 12th January, 2016. The first edition in 2015 was well attended by various industry leaders from Cadence, CVC, Mentor Graphics, AMD and many others along with academicians, students and practising engineers. Riding on […]

Dec
30
2015

Start-up street at IIT Delhi

On a cold winter morning, the national capital New Delhi woke upto a slow start on 29th Dec 2015. A mild breeze was adding to the chill temperature of 10 Degrees. IIT Delhi housed at “Hauz Khas” was buzzing with action thanks to the Alumni Day 2015 event. One of the most popular hangouts within the prestigious […]

Oct
24
2015

DVTalk Hyd Oct29, agenda

Riding on the success of initial few editions of VerifNews’ DVTalk event, we are glad to expand it to Hyderabad, Telangana, India this time. As usual with our start-up mode, finer details are still emerging. We have exciting topics and speakers lined up. Here is a draft agenda for your eyes only! Contact us via […]

Oct
10
2015

Mentor hosts a Formal Technology Seminar at Austin

Mentor Graphics, leading EDA company hosted a highly technical seminar entitled: “Formal Technology Seminar” at Austin on Oct 8th, 2015. Below is a quick trip report as captured by our VerifNews team. Agenda: Trends in Formal: What has Changed, What is Still Needed? — Harry Foster, Chief Verification Scientist How Mentor is Addressing Today’s Formal […]

Oct
05
2015

DVTalk Oct-6 agenda

Detailed agenda (close to final) for upcoming DVTalk event is below. It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basis. Please register here: http://goo.gl/forms/84IVLZGzYi   DVTalk Oct 6th, Tuesday Doubletree Hotel, Outer Ring Road, Sarjpaur Signal, Bangalore Track Time Topic Speaker Organization Women […]

Sep
21
2015

Start-up mentor, Atul Bhatia at DVCon India

As part of our DVCon India 2015 coverage, we are glad to bring excerpts from Atul Bhatia, an entrepreneur and a start-up mentor based in Delhi, India. Having led nSys design systems from the beginning to a successful exit (to Synopsys), Atul is a role model for many in India who aspire to develop VIPs and […]



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