Aug
25
2016

Debug automation: PinDown gets to file-level granularity in isolating bugs

Debug is one area that requires automation much more than available today. With Verdi’s NPI and emerging DDI (Debug Data Interface) becoming popular, third party “apps” to solve common debug problems are emerging fast in the market (e.g. RTGen from VerifWorks). One of the common tasks for regression analysis teams is to quickly narrow down […]

Feb
24
2016

Debug Data API Debut Meeting March 1st 

Message from Adam Sherer, Cadence on Debug-Data API meeting @DVCon US Fittingly, our first working proof of concept will happen on March 1st.  We will have a meeting of Debug Data API interested folks attending DVCon U.S. From 5:15p to 5:45p on Tuesday March 1st in the Fir Ballroom at the DoubleTree Hotel in San […]

Oct
05
2015

DVTalk Oct-6 agenda

Detailed agenda (close to final) for upcoming DVTalk event is below. It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basis. Please register here: http://goo.gl/forms/84IVLZGzYi   DVTalk Oct 6th, Tuesday Doubletree Hotel, Outer Ring Road, Sarjpaur Signal, Bangalore Track Time Topic Speaker Organization Women […]

Aug
26
2015

Exostiv Labs’s FPGA survey

Exostiv Labs is a division of Byte Paradigm sprl, a Belgium based company is looking for user views on FPGA debug and verification. Quick link to the survey is here: http://tinyurl.com/vn-fpga-survey There are two major kinds of FPGA users: Prototyping the next ASIC End product based on FPGA This survey caters to both the audience and will […]

Jun
01
2015

Cadence Introduces Indago Debug Platform, Improving Debugging Productivity by up to 50 Percent

SAN JOSE, Calif., 28 Apr 2015 HIGHLIGHTS: Patented root-cause analysis technology filters unneeded data to go beyond the source for a single bug to resolve the cause of all related bugs Includes three integrated debugging apps that provide a single synchronized debug solution Integrated open debug platform with third-party support enables multiple design and verification […]

Apr
01
2015

FPGA Verification done the smart way – the Bluepearl way!

Over the last half-a-decade, FPGAs have been becoming larger and larger in capacity and narrow/deep in technology nodes.  Given the cost advantages of FPGA, various companies that were erstwhile ASIC-only design houses have taken FPGA as the first step to production and/or prototyping. . As learnt in the ASIC domain, as designers’ ability to push more logic into a single […]

Mar
16
2015

Blue Pearl Software Introduces Debug Environment in Release 9.0 – Visual Debug and Verification Dramatically Shortens Design Cycle Time

SANTA CLARA, Calif., Feb. 11, 2015 (GLOBE NEWSWIRE) — via PRWEB – Blue Pearl Software, Inc., the provider of EDA software that accelerates IP and FPGA verification, announces release 9.0 of its software suite for Windows® and Linux® operating systems. It introduces the new Blue Pearl Debug Environment that significantly reduces the time it takes […]

Feb
19
2015

Blue Pearl Software Introduces Visual Debug and Verification in latest Release 9.0

Release 9.0 of the Blue Pearl Software Suite decreases development time with the new Debug Environment by shrinking the time to find and correct design mistakes. Key features include: Access to the HDL database once a design is loaded RTL to schematic cross probe Advanced tracing to specific design elements Hierarchical name search and Net […]

Jan
16
2015

At DVCon USA Cadence offers Debug tutorial to boost debug productivity using root cause analysis for RTL/TB and SoC

Sponsored Tutorial at DVCon 2015 Thursday, March 4 8:30am – 12:00pm Verification 501: Graduate-level Debug Tutorial Welcome returning students! In last year’s “Revolutionary Debug Techniques to Improve Verification Productivity” tutorial we focused on moving beyond printf to use interactive and post-processing techniques to make debugging environments like those built with UVM more efficient. This year’s tutorial […]

Jan
10
2015

Mentor release its latest Issue of Verification Horizons

High quality quarterly newsletter from Mentor Graphics covering deep Functional Verification topics such as: Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide – Fast Track to Productivity Using Questa VIP -Takes you through a new set of productivity features that we’ve named“EZ-VIP” that provides predefined sequences,configuration objects and wrapper modules to function as […]



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