Aug
26
2015

Exostiv Labs’s FPGA survey

Exostiv Labs is a division of Byte Paradigm sprl, a Belgium based company is looking for user views on FPGA debug and verification. Quick link to the survey is here: http://tinyurl.com/vn-fpga-survey There are two major kinds of FPGA users: Prototyping the next ASIC End product based on FPGA This survey caters to both the audience and will […]

Aug
04
2015

IEEE invites contributions for the upcoming UVM (IEEE P1800.2) standard

IEEE, the world’s largest professional association for the advancement of technology is into action that directly impacts (in a positive way) all the Design-Verification community across the globe. In-line with IEEE’s constant endeavours to advancing the technology, it is now accepting a donation from Accellera, an electronics industry standards committee on UVM (Universal Verification Methodology) to […]

Jun
08
2015

Synopsys buys Atrenta, builds on Verification Continuum

Around the industry’s most popular event, there is a BIG news for the VLSI/ASIC Design & Verification industry: Synopsys buys Atrenta:       As part of Synopsys’s new initiative to deliver a “Verification Continuum” (as reported by our VerifNews team at recent DVCon USA 2015, http://verifnews.org/2015/03/synopsys-sees-a-major-shift-left-approach-to-verification-at-dvcon-us-2015/) this is a very strong, bold and useful step for its […]

Jun
01
2015

Defacto to announce new release and share customer experience during DAC 2015

Defacto Technologies is excited to announce new releases of its products and share customer experience during DAC in San Francisco, June 8-10. Defacto team will be showcasing breakthrough RTL “Build&Signoff” EDA solutions with new releases of its STAR RTL and Gate-level Design tools. Please visit us at the booth #1902 for in-depth technical presentations. Send […]

Apr
24
2015

A photolog of Design&Reuse IP-SOC Day

As a follow-up to our earlier post covering recent D&R IP-SOC Day, here is a “photolog” (Or Photoblog: http://en.wikipedia.org/wiki/Photoblog) of the day’s talks. Hope you enjoy this innovative way of news coverage, courtesy VerifNews Organizer and main sponsors                            Srinivasan, MD of Mobiveil India (Chennai) […]

Apr
24
2015

D&R IP-SOC Days – Bangalore, 2015 event

– Bangalore, 2015 : Highlights                      – an EDA portal based out of Europe has been successfully running its “IP-SOC Days” for the past several years across the world. This year the Bangalore edition was held at the Park Plaza, ORR, Bangalore on March 25, 2015. Surprisingly not so well marketed on social media, this […]

Apr
01
2015

FPGA Verification done the smart way – the Bluepearl way!

Over the last half-a-decade, FPGAs have been becoming larger and larger in capacity and narrow/deep in technology nodes.  Given the cost advantages of FPGA, various companies that were erstwhile ASIC-only design houses have taken FPGA as the first step to production and/or prototyping. . As learnt in the ASIC domain, as designers’ ability to push more logic into a single […]

Mar
17
2015

Agnisys conquers SoC Register management, aims at more automation

Agnisys, the leader in Register automation solutions was exhibiting at DVCon US 2015. Our VerifNews team (VN) caught up with its CEO, Anupam Bakshi (AB) for a quick chat. Below is an excerpt. VN: How many years have you been exhibiting at DVCon? AB: About 4-5 years. VN: What are your key products/news around this DVCon? AB: iDesignspec […]

Mar
16
2015

Real Intent adds DO-254 checks, enhances SystemVerilog, VHDL support

One of the long standing independent EDA companies, Real Intent has significant updates at this year DVCon US. Our VerifNews team caught up with Graham Bell, Vice President of Marketing at Real Intent at their booth at the event. Here is a transcript:   VN: Tell us about your company please GB: Real Intent is a Verification […]

Mar
16
2015

Blue Pearl Software Introduces Debug Environment in Release 9.0 – Visual Debug and Verification Dramatically Shortens Design Cycle Time

SANTA CLARA, Calif., Feb. 11, 2015 (GLOBE NEWSWIRE) — via PRWEB – Blue Pearl Software, Inc., the provider of EDA software that accelerates IP and FPGA verification, announces release 9.0 of its software suite for Windows® and Linux® operating systems. It introduces the new Blue Pearl Debug Environment that significantly reduces the time it takes […]




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