Feb
24
2015

Longtime Veific Customer Rocketick Renews Parser Platform License

Longtime Verific Customer Rocketick Renews Parser Platform License SystemVerilog Parser Platform Serves as Front End to RocketSim Simulation AcceleratorALAMEDA, CA–(Marketwired – Feb 11, 2015)–Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers, today announced Rocketick Technologies Ltd., a leading provider of Verilog simulation acceleration solutions for chip verification, has renewed its license for Verific’s […]

Feb
19
2015

Blue Pearl Software Introduces Visual Debug and Verification in latest Release 9.0

Release 9.0 of the Blue Pearl Software Suite decreases development time with the new Debug Environment by shrinking the time to find and correct design mistakes. Key features include: Access to the HDL database once a design is loaded RTL to schematic cross probe Advanced tracing to specific design elements Hierarchical name search and Net […]

Jan
15
2015

Aldec’s DO-254 Webinar Jan. 22: Validation and Verification Process for DO-254

 Validation and Verification Process for DO-254  Date: Thursday, January 22, 2015 Register for India/EU 8.30 PM to 9.30 PM India time (4:00PM to 5:00PM CET) Register for US 11:00AM to 12:00PM PST (USA) Presenter: Randall Fulton, FAA Consultant DER Abstract: Requirements are central to the development process described in DO-254.  The Validation and Verification Process ensures that requirements […]

Dec
16
2014

Aldec offers Joint Webinar Dec. 18: Best Practices for DO-254 Requirements Traceability w/ Richland Technologies

Best Practices for DO-254 Requirements Traceability Jointly Presented with Richland Technologies  Date: Thursday, December 18, 2014 Register for EU 4:00PM to 5:00PM CET Register for US 11:00AM to 12:00PM PST   Abstract: DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements […]

Dec
13
2014

Top 5 Reasons to be Excited About Mixed-Signal Verification in 2015 – Cadence

Reason 1: Mixed-signal is dominant Reason 2: Innovation in many directions, mostly mixed-signal applications Reason 3: Trends are pushing the limits of established design practices Reason 4: The tipping point accelerants are catching fire Reason 5: Convergence of analog and digital design Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping […]

Nov
27
2014

Deepchip publishes “First user look at Defactos RTL & gate editing, coding, ECO tool”

Hi, John,Please keep me and my company anonymous.I saw that you were curious about Defacto in your DAC Cheesy Must See Listthis year. We bought Defacto STAR RTL Platform about 3 years ago after a 3 month eval,and have been using it ever since.STAR RTL is like a “designers toolbox”, with a lot of different […]

Nov
21
2014

New IP Prototyping Kits for 10 Interface Protocols

DesignWare IP Prototyping Kits for 10 Interface ProtocolsAccelerate Prototyping, Software Development and Integration of USB 3.0, SSIC, PCI Express 2.0 & 3.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI 2.0, and JEDEC UFS Protocols IP into SoCs via New IP Prototyping Kits for 10 Interface Protocols.

Nov
14
2014

Aldec Delivers Efficient Verification with Requirements-based, User-defined Test Plan in Coverage – 2014-11-12 – Newsroom – Company – Aldec

Henderson, NV – November 12, 2014 – Aldec, Inc., announces the latest release of its mixed-language, advanced verification platform, Riviera-PRO™ 2014.10. This release of Riviera-PRO delivers speed and efficiency to the verification process by enhancing coverage metrics. Riviera-PRO has long supported UCIS-compatible coverage databases, and the latest release enables a new approach by linking requirements-based, user-defined test […]

Nov
11
2014

Webinar: The Complete Solution for Register Specification, Design and Verification

Agnisys Webinar: The Complete Solution for Register Specification, Design and Verification   When: Wednesday, November 12, 1:00 to 2:00 PM Eastern Standard Time   Who should attend: Spec Writers, Architects, Designers, Verification Engineers, Firmware Developers   What will you see: How to develop correct-by-construction register definitions from a single register specification Auto-generation of a range of outputs from a […]

Nov
11
2014

10 things to know about memory verification: Introducing Synopsys Memory VIP

On-demand webinar: Attendees Will Learn: Dynamic part selection; no need for re-compilation when selecting new part Intelligent, built-in JEDEC compliant Protocol and timing checks Pre-defined CoverGroups for Memory State transition, training and power down modes, and more Direct testbench access to the Memory Core for peek, poke, and set/get/clear any memory location attributes Error injections […]




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