Feb
24
2015

Longtime Veific Customer Rocketick Renews Parser Platform License

Longtime Verific Customer Rocketick Renews Parser Platform License SystemVerilog Parser Platform Serves as Front End to RocketSim Simulation AcceleratorALAMEDA, CA–(Marketwired – Feb 11, 2015)–Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers, today announced Rocketick Technologies Ltd., a leading provider of Verilog simulation acceleration solutions for chip verification, has renewed its license for Verific’s […]

Feb
19
2015

Blue Pearl Software Introduces Visual Debug and Verification in latest Release 9.0

Release 9.0 of the Blue Pearl Software Suite decreases development time with the new Debug Environment by shrinking the time to find and correct design mistakes. Key features include: Access to the HDL database once a design is loaded RTL to schematic cross probe Advanced tracing to specific design elements Hierarchical name search and Net […]

Aug
11
2014

Call for Tutorials | DVCon USA 2015

DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and e, as well as general purpose languages such […]




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