Our next DVTalk event will be held at BMS college of Engineering, Bangalore. BMS is holding a 3-day hands-on workshop on “Advances in Verification Methodologies” from Jun 13-15 2016. VerifWorks will be delivering a session on SystemVerilog Assertions and Go2UVM traces for assertions. Complete agenda is below:
Category: EDA
Dec
30
2015
Start-up street at IIT Delhi
On a cold winter morning, the national capital New Delhi woke upto a slow start on 29th Dec 2015. A mild breeze was adding to the chill temperature of 10 Degrees. IIT Delhi housed at “Hauz Khas” was buzzing with action thanks to the Alumni Day 2015 event. One of the most popular hangouts within the prestigious […]
Oct
24
2015
DVTalk Hyd Oct29, agenda
Riding on the success of initial few editions of VerifNews’ DVTalk event, we are glad to expand it to Hyderabad, Telangana, India this time. As usual with our start-up mode, finer details are still emerging. We have exciting topics and speakers lined up. Here is a draft agenda for your eyes only! Contact us via […]
Oct
10
2015
Mentor hosts a Formal Technology Seminar at Austin
Mentor Graphics, leading EDA company hosted a highly technical seminar entitled: “Formal Technology Seminar” at Austin on Oct 8th, 2015. Below is a quick trip report as captured by our VerifNews team. Agenda: Trends in Formal: What has Changed, What is Still Needed? — Harry Foster, Chief Verification Scientist How Mentor is Addressing Today’s Formal […]
Oct
05
2015
DVTalk Oct-6 agenda
Detailed agenda (close to final) for upcoming DVTalk event is below. It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basis. Please register here: http://goo.gl/forms/84IVLZGzYi DVTalk Oct 6th, Tuesday Doubletree Hotel, Outer Ring Road, Sarjpaur Signal, Bangalore Track Time Topic Speaker Organization Women […]
Sep
02
2015
DVCon India countdown – views from Shivayogi, verification consultant
In this edition of my DVCon India 2015 countdown, I bring views from Shivayogi Kerudi, a seasoned verification consultant. It is this kind of passionate verification engineers that this event is aimed at addressing, grooming and leveraging on their experience in future. So I dedicate this post to all those passionate DV folks out there! DVCon […]
Aug
26
2015
Exostiv Labs’s FPGA survey
Exostiv Labs is a division of Byte Paradigm sprl, a Belgium based company is looking for user views on FPGA debug and verification. Quick link to the survey is here: http://tinyurl.com/vn-fpga-survey There are two major kinds of FPGA users: Prototyping the next ASIC End product based on FPGA This survey caters to both the audience and will […]
Aug
26
2015
Accellera Aug 2015 Newsletter is out – read about new standards, events etc.
Community Newsletter: August 2015 IN THIS ISSUE:Message from the ChairUVM 1.2 joins growing list of standards contributed to IEEE-SADVCon Global FocusThe latest updates on DVCon India, Europe, and U.SSystemC JapanEngineers in Japan enjoy a full day of SystemC educationAccellera in the NewsUVM 1.2 delivered to IEEE-SA and SCE-MI 2.3 updatesScheduled Working Group MeetingPortable Stimulus Working […]
Aug
24
2015
UVM-ML Open Architecture – Accellera Systems Initiative Forums
UVM-ML Open Architecture – version 1.5.1Enabling Multi-Language and Multi-Framework VerificationAug 23th, 2015General OverviewUniversal Verification Methodology Multi-Language (UVM-ML) provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages […]
Aug
20
2015
DVCon India countdown – views from Invionics, Canada
As part of my DVCon India 2015 countdown, I recently had a chat with Dr. Brad Quinton, CEO at Invionics Inc. Invio as a product from Invionics provides a custom EDA platform for semiconductor design houses to build own tools on need basis. As a serial entrepreneur I am glad to […]
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