Jun
08
2015

Synopsys buys Atrenta, builds on Verification Continuum

Around the industry’s most popular event, there is a BIG news for the VLSI/ASIC Design & Verification industry: Synopsys buys Atrenta:       As part of Synopsys’s new initiative to deliver a “Verification Continuum” (as reported by our VerifNews team at recent DVCon USA 2015, http://verifnews.org/2015/03/synopsys-sees-a-major-shift-left-approach-to-verification-at-dvcon-us-2015/) this is a very strong, bold and useful step for its […]

Apr
01
2015

FPGA Verification done the smart way – the Bluepearl way!

Over the last half-a-decade, FPGAs have been becoming larger and larger in capacity and narrow/deep in technology nodes.  Given the cost advantages of FPGA, various companies that were erstwhile ASIC-only design houses have taken FPGA as the first step to production and/or prototyping. . As learnt in the ASIC domain, as designers’ ability to push more logic into a single […]

Mar
16
2015

Real Intent adds DO-254 checks, enhances SystemVerilog, VHDL support

One of the long standing independent EDA companies, Real Intent has significant updates at this year DVCon US. Our VerifNews team caught up with Graham Bell, Vice President of Marketing at Real Intent at their booth at the event. Here is a transcript:   VN: Tell us about your company please GB: Real Intent is a Verification […]

Mar
16
2015

Blue Pearl Software Introduces Debug Environment in Release 9.0 – Visual Debug and Verification Dramatically Shortens Design Cycle Time

SANTA CLARA, Calif., Feb. 11, 2015 (GLOBE NEWSWIRE) — via PRWEB – Blue Pearl Software, Inc., the provider of EDA software that accelerates IP and FPGA verification, announces release 9.0 of its software suite for Windows® and Linux® operating systems. It introduces the new Blue Pearl Debug Environment that significantly reduces the time it takes […]




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