Jun
13
2016

DVTalk on SystemVerilog Assertions & UVM at BMS College, Bangalore

Our next DVTalk event will be held at BMS college of Engineering, Bangalore.  BMS is holding a 3-day hands-on workshop on “Advances in Verification Methodologies” from Jun 13-15 2016. VerifWorks will be delivering a session on SystemVerilog Assertions and Go2UVM traces for assertions. Complete agenda is below:

Feb
25
2016

DVCon 2016 is next week – preview of our contributions

DVCon 2016 is next week – preview of our contributions The primary annual technical carnival of the VLSI & EDA industry focusing on front-end design is DVCon. Since its inception several years ago (a very good history of DVCon is at: DVCon History), DVCon has spread its wings across the globe with India and EU editions […]

Oct
05
2015

DVTalk Oct-6 agenda

Detailed agenda (close to final) for upcoming DVTalk event is below. It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basis. Please register here: http://goo.gl/forms/84IVLZGzYi   DVTalk Oct 6th, Tuesday Doubletree Hotel, Outer Ring Road, Sarjpaur Signal, Bangalore Track Time Topic Speaker Organization Women […]

Aug
04
2015

IEEE invites contributions for the upcoming UVM (IEEE P1800.2) standard

IEEE, the world’s largest professional association for the advancement of technology is into action that directly impacts (in a positive way) all the Design-Verification community across the globe. In-line with IEEE’s constant endeavours to advancing the technology, it is now accepting a donation from Accellera, an electronics industry standards committee on UVM (Universal Verification Methodology) to […]

Jun
29
2015

Benefits of native UVM VIP

Benefits of native UVM VIP     Srinivasan Venkataramanan, Chief Editor, http://www.VerifNews.org Shankar Hemmady Ever since the birth of Accellera UVM standard (and now on its way to becoming an IEEE 1800.2 standard), several companies have announced Verification Intellectual Properties (VIPs). The primary objective of UVM standardization committee was to develop a set of base […]

Jun
01
2015

Truechip announces CVIP for HDMI

May 27, 2015 – Truechip Solutions, the verification IP specialist, announced today that it has shipped early adopter version of its HDMI 2.0Comprehensive Verification IP (CVIP) to its partners in the early adoption program. This CVIP is natively developed in SystemVerilog (UVM) and is architected such that a single VIP is able to provide comprehensive, […]

Mar
17
2015

Agnisys conquers SoC Register management, aims at more automation

Agnisys, the leader in Register automation solutions was exhibiting at DVCon US 2015. Our VerifNews team (VN) caught up with its CEO, Anupam Bakshi (AB) for a quick chat. Below is an excerpt. VN: How many years have you been exhibiting at DVCon? AB: About 4-5 years. VN: What are your key products/news around this DVCon? AB: iDesignspec […]

Jan
29
2015

VerifLabs announces a free DIY style workshop on SystemVerilog constraints

VerifLabs, a new venture under CVC is proud to announce a workshop on SystemVerilog constraints. This is a DIY – Do-It Yourself style workshop and NOT a training! You need to know the lingo, construct and have verification background to “Do-It”. Date: Jan 31, 2015 Time: 10 AM – 5 PM (walkin anytime, will allow 2-3 […]

Jan
10
2015

Mentor release its latest Issue of Verification Horizons

High quality quarterly newsletter from Mentor Graphics covering deep Functional Verification topics such as: Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide – Fast Track to Productivity Using Questa VIP -Takes you through a new set of productivity features that we’ve named“EZ-VIP” that provides predefined sequences,configuration objects and wrapper modules to function as […]

Dec
15
2014

DVClub Austin and MTV 2014 Joint Event: December 17

DVClub Austin and MTV 2014 Joint Event: December 17 We are pleased to once again join forces with MTV 2014 for our December event. In addition to our usual lunch, networking, and presentation, we will enjoy two tutorial sessions by industry leaders. When registering, you have the option to attend just the lunch and first […]



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