Sep
16
2018

Verification Leaders unleash UVM via book, examples and workshops

VLSI Design-Verification as a field is booming over the last decade. More so with the advent of UVM (Universal Verification Methodology) as a standard from Accellera back in early 2000-s. UVM has grown leaps and bounds and has been adopted by almost every ASIC design team across the globe. Growth of industries like IoT, automobile […]

Apr
17
2018

Event alert – “India UVM Day” on Apr 24, 2018

For all the Design-Verification engineers out there in India, an important event alert! As a country with maximum number of Design Verification engineers in the world, there is more reason to cherish – The “India UVM Day” is here in Bangalore on 24-Apr-2018. Register today for FREE @ https://tinyurl.com/ieee-uvm Here is a brief of what […]

Apr
09
2018

DVTalk – Apr’18: VLSI Career workshop, IEEE UVM and more

Our next episode of DVTalk is here! Welcome to DVTalk April-2018. In this episode we are thrilled to partner with leading VLSI & EDA companies and standard committee to bring you the latest in this field. It is free to attend, but registration is mandatory. As seats gets filled quickly, we suggest you register right-away […]

Apr
07
2018

Exciting times in the world of VLSI Design-Verification!

To all our readers, sorry for the silence over last few quarters. Our content writers had moved on and our funding team got busy with other projects. So here we are at a crucial period of time in this world of Design-Verification. With new standards in the making Accellera Systems Initiative, this industry’s premier standards […]

Jun
13
2016

DVTalk on SystemVerilog Assertions & UVM at BMS College, Bangalore

Our next DVTalk event will be held at BMS college of Engineering, Bangalore.  BMS is holding a 3-day hands-on workshop on “Advances in Verification Methodologies” from Jun 13-15 2016. VerifWorks will be delivering a session on SystemVerilog Assertions and Go2UVM traces for assertions. Complete agenda is below:

Feb
25
2016

DVCon 2016 is next week – preview of our contributions

DVCon 2016 is next week – preview of our contributions The primary annual technical carnival of the VLSI & EDA industry focusing on front-end design is DVCon. Since its inception several years ago (a very good history of DVCon is at: DVCon History), DVCon has spread its wings across the globe with India and EU editions […]

Oct
05
2015

DVTalk Oct-6 agenda

Detailed agenda (close to final) for upcoming DVTalk event is below. It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basis. Please register here: http://goo.gl/forms/84IVLZGzYi   DVTalk Oct 6th, Tuesday Doubletree Hotel, Outer Ring Road, Sarjpaur Signal, Bangalore Track Time Topic Speaker Organization Women […]

Aug
04
2015

IEEE invites contributions for the upcoming UVM (IEEE P1800.2) standard

IEEE, the world’s largest professional association for the advancement of technology is into action that directly impacts (in a positive way) all the Design-Verification community across the globe. In-line with IEEE’s constant endeavours to advancing the technology, it is now accepting a donation from Accellera, an electronics industry standards committee on UVM (Universal Verification Methodology) to […]

Jun
29
2015

Benefits of native UVM VIP

Benefits of native UVM VIP     Srinivasan Venkataramanan, Chief Editor, http://www.VerifNews.org Shankar Hemmady Ever since the birth of Accellera UVM standard (and now on its way to becoming an IEEE 1800.2 standard), several companies have announced Verification Intellectual Properties (VIPs). The primary objective of UVM standardization committee was to develop a set of base […]

Jun
01
2015

Truechip announces CVIP for HDMI

May 27, 2015 – Truechip Solutions, the verification IP specialist, announced today that it has shipped early adopter version of its HDMI 2.0Comprehensive Verification IP (CVIP) to its partners in the early adoption program. This CVIP is natively developed in SystemVerilog (UVM) and is architected such that a single VIP is able to provide comprehensive, […]



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