Mar
17
2015

Agnisys conquers SoC Register management, aims at more automation

Agnisys, the leader in Register automation solutions was exhibiting at DVCon US 2015. Our VerifNews team (VN) caught up with its CEO, Anupam Bakshi (AB) for a quick chat. Below is an excerpt. VN: How many years have you been exhibiting at DVCon? AB: About 4-5 years. VN: What are your key products/news around this DVCon? AB: iDesignspec […]

Jan
29
2015

VerifLabs announces a free DIY style workshop on SystemVerilog constraints

VerifLabs, a new venture under CVC is proud to announce a workshop on SystemVerilog constraints. This is a DIY – Do-It Yourself style workshop and NOT a training! You need to know the lingo, construct and have verification background to “Do-It”. Date: Jan 31, 2015 Time: 10 AM – 5 PM (walkin anytime, will allow 2-3 […]

Jan
10
2015

Mentor release its latest Issue of Verification Horizons

High quality quarterly newsletter from Mentor Graphics covering deep Functional Verification topics such as: Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide – Fast Track to Productivity Using Questa VIP -Takes you through a new set of productivity features that we’ve named“EZ-VIP” that provides predefined sequences,configuration objects and wrapper modules to function as […]

Dec
15
2014

DVClub Austin and MTV 2014 Joint Event: December 17

DVClub Austin and MTV 2014 Joint Event: December 17 We are pleased to once again join forces with MTV 2014 for our December event. In addition to our usual lunch, networking, and presentation, we will enjoy two tutorial sessions by industry leaders. When registering, you have the option to attend just the lunch and first […]

Nov
20
2014

SystemVerilog-UVM, Verification “Hackathon” » GO 2 UVM – for VLSI Designers

Are you a die-hard Verification fan? Are you looking to improve on your UVM skills in a real “bug hunting” event?VerifLabs, www.veriflabs.com, a new venture from CVC www.cvcblr.com is pleased to announce “SystemVerilog-UVM, Verification Hackathon”. As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going […]

Nov
14
2014

Aldec Delivers Efficient Verification with Requirements-based, User-defined Test Plan in Coverage – 2014-11-12 – Newsroom – Company – Aldec

Henderson, NV – November 12, 2014 – Aldec, Inc., announces the latest release of its mixed-language, advanced verification platform, Riviera-PRO™ 2014.10. This release of Riviera-PRO delivers speed and efficiency to the verification process by enhancing coverage metrics. Riviera-PRO has long supported UCIS-compatible coverage databases, and the latest release enables a new approach by linking requirements-based, user-defined test […]

Nov
11
2014

Webinar: The Complete Solution for Register Specification, Design and Verification

Agnisys Webinar: The Complete Solution for Register Specification, Design and Verification   When: Wednesday, November 12, 1:00 to 2:00 PM Eastern Standard Time   Who should attend: Spec Writers, Architects, Designers, Verification Engineers, Firmware Developers   What will you see: How to develop correct-by-construction register definitions from a single register specification Auto-generation of a range of outputs from a […]

Oct
13
2014

Cadence blog on “10 features likely to be unknown by many Incisive users”

Very interesting read from recent CDN blog. From our quick browse, wearing our technical hat, the following are more useful for SV/UVM folks:   5. IEEE 1801 (aka UPF) Power Supply Network Browser: The easy way to debug your UPF power supply network. 6. Quick diff in the waveform viewer: A fast way to detect unexpected signal differences. 7. UVM […]

Sep
28
2014

“Make Apps campaign” comes real at DVCon India with VC Apps

In case you missed it, the Indian Prime Minister Shri. Narendra Modi announced the “Make in India” campaign last week (See: bbc.in/1uSVBwc) Though in his true vision it is primarily intended for Manufacturing sector,  a bunch of smart entrepreneurs in SW/IT world tagged onto it and suggested that “Make apps in India” should also be part […]

Sep
23
2014

VerifLabs’s approach to Coverage closure with Constrained Random flow

Do you use Constrained Random & Coverage Driven Verification? If yes, you don’t want to miss this. http://goo.gl/3mcafL  



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