Functional verification is becoming a bottleneck and is affecting all design teams. It’s in a chip’s best interest that you as a design engineer make an effort to boost verification productivity. Here, we provide 10 simple tips that will significantly boost your IP verification productivity. via 10 Useful Tips for Design Teams To Boost Verification […]
Go2UVM.org, the premier UVM learning site has published a handy quick start guide to UVM register modelling for standard IPs. It also promises to make available to users a series of UVM Register models for popular IPs based on OpenCores shortly. UVM register model creation – just a few clicks away » GO 2 UVM – […]
CVC releases free resource – SystemVerilog interfaces, step-by-step guide » GO 2 UVM – for VLSI Designers
CVC along with Aldec releases a recorded webinar on SystemVerilog Interface. Making your first step into UVM? You absolutely need to create a SystemVerilog interface so that your UVM testbench can talk to your DUT. Want to learn how to do it step-by-step? Learn from this 1 hour webinar archive delivered by Srinivasan Venkataramanan, Chief […]
We are excited to announce the availability of Aldec’s Riviera-PRO EDU simulator on EDA Playground. Riviera-PRO is a full-featured commercial simulator that has full support for SystemVerilog, VHDL, and SystemC. The goal of EDA Playground has always been to accelerate learning and give engineers immedate hands-on exposure to simulating HDLs. Finally, for the first time […]
In UVM, sequences can provide a wealth of functionality beyond initiating stimulus on a particular interface. Often designs require the verification environment to respond to traffic from the DUT, and sequences can model this behavior as well. By modeling responders through the use of Slave Sequences, UVM enhances reuse by encapsulating the functionality in sequences […]
After successful tests and trials at several companies, official UVM 1.2 release is now publicly available for one and all! Download UVM 1.2 Tar Ball Accellera Systems Initiative released UVM 1.2 today, June 24, 2014. It’s available for immediate download. There is also a new forum open on the Accellera site to collect your feedback and […]
The Design and Verification Conference & Exhibition India DVCon India is a new technical conference in India targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon India is similar to the successful DVCon United States […]
Global Leader In Flash Memory Storage Adopts Arrow Devices’ JEDEC UFS and MIPI Solutions | Arrow Devices
Global Leader In Flash Memory Storage Adopts Arrow Devices’ JEDEC UFS and MIPI Solutions via Global Leader In Flash Memory Storage Adopts Arrow Devices’ JEDEC UFS and MIPI Solutions | Arrow Devices.
IP Integration: Not a Simple Operation | Systems Design Engineering Community.
AMIQ EDA Releases Version 3.5 of the Design and Verification Tools (DVT) IDE via AMIQ EDA Releases Version 3.5 of the Design and Verification Tools (DVT) IDE.