Sep
16
2018

Verification Leaders unleash UVM via book, examples and workshops

VLSI Design-Verification as a field is booming over the last decade. More so with the advent of UVM (Universal Verification Methodology) as a standard from Accellera back in early 2000-s. UVM has grown leaps and bounds and has been adopted by almost every ASIC design team across the globe. Growth of industries like IoT, automobile […]

Apr
17
2018

Event alert – “India UVM Day” on Apr 24, 2018

For all the Design-Verification engineers out there in India, an important event alert! As a country with maximum number of Design Verification engineers in the world, there is more reason to cherish – The “India UVM Day” is here in Bangalore on 24-Apr-2018. Register today for FREE @ https://tinyurl.com/ieee-uvm Here is a brief of what […]

Apr
09
2018

DVTalk – Apr’18: VLSI Career workshop, IEEE UVM and more

Our next episode of DVTalk is here! Welcome to DVTalk April-2018. In this episode we are thrilled to partner with leading VLSI & EDA companies and standard committee to bring you the latest in this field. It is free to attend, but registration is mandatory. As seats gets filled quickly, we suggest you register right-away […]

Apr
07
2018

Exciting times in the world of VLSI Design-Verification!

To all our readers, sorry for the silence over last few quarters. Our content writers had moved on and our funding team got busy with other projects. So here we are at a crucial period of time in this world of Design-Verification. With new standards in the making Accellera Systems Initiative, this industry’s premier standards […]

Sep
10
2016

Hardware-Assisted Verification seminar – Aldec, CVC & IISc – notes

Aldec, Inc., an industry-leading Electronic Design Automation (EDA) company recently hosted a technical seminar on “Hardware-Assisted Verification” in Bangalore, India on Sep 08, 2016. The full-day event had multiple high-profile speakers from the industry and academia: Below is a brief summary of the day’s proceedings as captured by our team member! Introduction to Hardware Assisted […]

Aug
28
2016

DVTalk Aug 2016 – VLSI industry & UVM adoption

VerifNews is glad to announce  a new #DVTalk session titled: VLSI industry & UVM adoption Brief agenda: 1.       VLSI industry overview . 2.       UVM apps and open-source approach (Courtesy: www.go2uvm.org) 3.       Hidden gems of UVM debug This is an exclusive DVTalk event being held at Amrita Bengaluru Campus. Date: Aug 31st 2016 Time: 10.30-12.30 Stay tuned for event […]

Aug
11
2016

Hardware-Assisted Verification – Free Seminar Bangalore

 Aldec, Inc., an industry-leading Electronic Design Automation (EDA) company is glad to host a technical seminar on “Hardware-Assisted Verification” in Bangalore, India on Sep 08, 2016. The full-day event has multiple high-profile speakers from the industry and academia: More details and registration link can be found at: https://www.aldec.com/en/events/736 It is FREE of cost, but registration […]

Jun
13
2016

DVTalk on SystemVerilog Assertions & UVM at BMS College, Bangalore

Our next DVTalk event will be held at BMS college of Engineering, Bangalore.  BMS is holding a 3-day hands-on workshop on “Advances in Verification Methodologies” from Jun 13-15 2016. VerifWorks will be delivering a session on SystemVerilog Assertions and Go2UVM traces for assertions. Complete agenda is below:

Feb
25
2016

DVCon 2016 is next week – preview of our contributions

DVCon 2016 is next week – preview of our contributions The primary annual technical carnival of the VLSI & EDA industry focusing on front-end design is DVCon. Since its inception several years ago (a very good history of DVCon is at: DVCon History), DVCon has spread its wings across the globe with India and EU editions […]

Oct
24
2015

DVTalk Hyd Oct29, agenda

Riding on the success of initial few editions of VerifNews’ DVTalk event, we are glad to expand it to Hyderabad, Telangana, India this time. As usual with our start-up mode, finer details are still emerging. We have exciting topics and speakers lined up. Here is a draft agenda for your eyes only! Contact us via […]



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