Sep
10
2016

Hardware-Assisted Verification seminar – Aldec, CVC & IISc – notes

Aldec, Inc., an industry-leading Electronic Design Automation (EDA) company recently hosted a technical seminar on “Hardware-Assisted Verification” in Bangalore, India on Sep 08, 2016. The full-day event had multiple high-profile speakers from the industry and academia: Below is a brief summary of the day’s proceedings as captured by our team member! Introduction to Hardware Assisted […]

Aug
28
2016

DVTalk Aug 2016 – VLSI industry & UVM adoption

VerifNews is glad to announce  a new #DVTalk session titled: VLSI industry & UVM adoption Brief agenda: 1.       VLSI industry overview . 2.       UVM apps and open-source approach (Courtesy: www.go2uvm.org) 3.       Hidden gems of UVM debug This is an exclusive DVTalk event being held at Amrita Bengaluru Campus. Date: Aug 31st 2016 Time: 10.30-12.30 Stay tuned for event […]

Aug
11
2016

Hardware-Assisted Verification – Free Seminar Bangalore

 Aldec, Inc., an industry-leading Electronic Design Automation (EDA) company is glad to host a technical seminar on “Hardware-Assisted Verification” in Bangalore, India on Sep 08, 2016. The full-day event has multiple high-profile speakers from the industry and academia: More details and registration link can be found at: https://www.aldec.com/en/events/736 It is FREE of cost, but registration […]

Jun
13
2016

DVTalk on SystemVerilog Assertions & UVM at BMS College, Bangalore

Our next DVTalk event will be held at BMS college of Engineering, Bangalore.  BMS is holding a 3-day hands-on workshop on “Advances in Verification Methodologies” from Jun 13-15 2016. VerifWorks will be delivering a session on SystemVerilog Assertions and Go2UVM traces for assertions. Complete agenda is below:

Feb
25
2016

DVCon 2016 is next week – preview of our contributions

DVCon 2016 is next week – preview of our contributions The primary annual technical carnival of the VLSI & EDA industry focusing on front-end design is DVCon. Since its inception several years ago (a very good history of DVCon is at: DVCon History), DVCon has spread its wings across the globe with India and EU editions […]

Oct
24
2015

DVTalk Hyd Oct29, agenda

Riding on the success of initial few editions of VerifNews’ DVTalk event, we are glad to expand it to Hyderabad, Telangana, India this time. As usual with our start-up mode, finer details are still emerging. We have exciting topics and speakers lined up. Here is a draft agenda for your eyes only! Contact us via […]

Oct
05
2015

DVTalk Oct-6 agenda

Detailed agenda (close to final) for upcoming DVTalk event is below. It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basis. Please register here: http://goo.gl/forms/84IVLZGzYi   DVTalk Oct 6th, Tuesday Doubletree Hotel, Outer Ring Road, Sarjpaur Signal, Bangalore Track Time Topic Speaker Organization Women […]

Aug
04
2015

IEEE invites contributions for the upcoming UVM (IEEE P1800.2) standard

IEEE, the world’s largest professional association for the advancement of technology is into action that directly impacts (in a positive way) all the Design-Verification community across the globe. In-line with IEEE’s constant endeavours to advancing the technology, it is now accepting a donation from Accellera, an electronics industry standards committee on UVM (Universal Verification Methodology) to […]

Jun
29
2015

Benefits of native UVM VIP

Benefits of native UVM VIP     Srinivasan Venkataramanan, Chief Editor, http://www.VerifNews.org Shankar Hemmady Ever since the birth of Accellera UVM standard (and now on its way to becoming an IEEE 1800.2 standard), several companies have announced Verification Intellectual Properties (VIPs). The primary objective of UVM standardization committee was to develop a set of base […]

Jun
01
2015

Truechip announces CVIP for HDMI

May 27, 2015 – Truechip Solutions, the verification IP specialist, announced today that it has shipped early adopter version of its HDMI 2.0Comprehensive Verification IP (CVIP) to its partners in the early adoption program. This CVIP is natively developed in SystemVerilog (UVM) and is architected such that a single VIP is able to provide comprehensive, […]



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