Mar
17
2015

Agnisys conquers SoC Register management, aims at more automation

Agnisys, the leader in Register automation solutions was exhibiting at DVCon US 2015. Our VerifNews team (VN) caught up with its CEO, Anupam Bakshi (AB) for a quick chat. Below is an excerpt. VN: How many years have you been exhibiting at DVCon? AB: About 4-5 years. VN: What are your key products/news around this DVCon? AB: iDesignspec […]

Dec
09
2014

UVM-ML Open Architecture – Accellera Systems Initiative Forums

Universal Verification Methodology Multi-Language UVM-ML provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages and methodologies.This release of the UVM-ML implementation is the result of collaboration […]

Nov
20
2014

SystemVerilog-UVM, Verification “Hackathon” » GO 2 UVM – for VLSI Designers

Are you a die-hard Verification fan? Are you looking to improve on your UVM skills in a real “bug hunting” event?VerifLabs, www.veriflabs.com, a new venture from CVC www.cvcblr.com is pleased to announce “SystemVerilog-UVM, Verification Hackathon”. As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going […]

Nov
14
2014

Aldec Delivers Efficient Verification with Requirements-based, User-defined Test Plan in Coverage – 2014-11-12 – Newsroom – Company – Aldec

Henderson, NV – November 12, 2014 – Aldec, Inc., announces the latest release of its mixed-language, advanced verification platform, Riviera-PRO™ 2014.10. This release of Riviera-PRO delivers speed and efficiency to the verification process by enhancing coverage metrics. Riviera-PRO has long supported UCIS-compatible coverage databases, and the latest release enables a new approach by linking requirements-based, user-defined test […]

Nov
11
2014

Webinar: The Complete Solution for Register Specification, Design and Verification

Agnisys Webinar: The Complete Solution for Register Specification, Design and Verification   When: Wednesday, November 12, 1:00 to 2:00 PM Eastern Standard Time   Who should attend: Spec Writers, Architects, Designers, Verification Engineers, Firmware Developers   What will you see: How to develop correct-by-construction register definitions from a single register specification Auto-generation of a range of outputs from a […]

Nov
11
2014

10 things to know about memory verification: Introducing Synopsys Memory VIP

On-demand webinar: Attendees Will Learn: Dynamic part selection; no need for re-compilation when selecting new part Intelligent, built-in JEDEC compliant Protocol and timing checks Pre-defined CoverGroups for Memory State transition, training and power down modes, and more Direct testbench access to the Memory Core for peek, poke, and set/get/clear any memory location attributes Error injections […]

Nov
07
2014

Verifying ARM AMBA® 5 CHI Interconnect-Based SoCs Using Next-Generation VIP

To meet the low-power, performance and functionality demands of advanced electronics products, virtually every SoC designed today is a multicore SoC. In this environment, on-chip cache memory plays a critical role, as memory architecture is fundamental in determining system performance.Historically, CPU speed has outpaced memory speed. This performance gap led to the use of on-chip […]

Oct
13
2014

Cadence blog on “10 features likely to be unknown by many Incisive users”

Very interesting read from recent CDN blog. From our quick browse, wearing our technical hat, the following are more useful for SV/UVM folks:   5. IEEE 1801 (aka UPF) Power Supply Network Browser: The easy way to debug your UPF power supply network. 6. Quick diff in the waveform viewer: A fast way to detect unexpected signal differences. 7. UVM […]

Oct
01
2014

Quality Verification papers for free download, CDNLive India 2014 

CDNLive India 2014 — Conference ProceedingsConference proceedings are now available for download. Use your cadence.com user account to log in. via CDNLive India 2014 .

Sep
28
2014

“Make Apps campaign” comes real at DVCon India with VC Apps

In case you missed it, the Indian Prime Minister Shri. Narendra Modi announced the “Make in India” campaign last week (See: bbc.in/1uSVBwc) Though in his true vision it is primarily intended for Manufacturing sector,  a bunch of smart entrepreneurs in SW/IT world tagged onto it and suggested that “Make apps in India” should also be part […]



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