To meet the low-power, performance and functionality demands of advanced electronics products, virtually every SoC designed today is a multicore SoC. In this environment, on-chip cache memory plays a critical role, as memory architecture is fundamental in determining system performance.Historically, CPU speed has outpaced memory speed. This performance gap led to the use of on-chip […]
Very interesting read from recent CDN blog. From our quick browse, wearing our technical hat, the following are more useful for SV/UVM folks: 5. IEEE 1801 (aka UPF) Power Supply Network Browser: The easy way to debug your UPF power supply network. 6. Quick diff in the waveform viewer: A fast way to detect unexpected signal differences. 7. UVM […]
CDNLive India 2014 — Conference ProceedingsConference proceedings are now available for download. Use your cadence.com user account to log in. via CDNLive India 2014 .
In case you missed it, the Indian Prime Minister Shri. Narendra Modi announced the “Make in India” campaign last week (See: bbc.in/1uSVBwc) Though in his true vision it is primarily intended for Manufacturing sector, a bunch of smart entrepreneurs in SW/IT world tagged onto it and suggested that “Make apps in India” should also be part […]
Go2UVM.org, the premier UVM learning site has published a handy quick start guide to UVM register modelling for standard IPs. It also promises to make available to users a series of UVM Register models for popular IPs based on OpenCores shortly. UVM register model creation – just a few clicks away » GO 2 UVM – […]
CVC releases free resource – SystemVerilog interfaces, step-by-step guide » GO 2 UVM – for VLSI Designers
CVC along with Aldec releases a recorded webinar on SystemVerilog Interface. Making your first step into UVM? You absolutely need to create a SystemVerilog interface so that your UVM testbench can talk to your DUT. Want to learn how to do it step-by-step? Learn from this 1 hour webinar archive delivered by Srinivasan Venkataramanan, Chief […]
We are excited to announce the availability of Aldec’s Riviera-PRO EDU simulator on EDA Playground. Riviera-PRO is a full-featured commercial simulator that has full support for SystemVerilog, VHDL, and SystemC. The goal of EDA Playground has always been to accelerate learning and give engineers immedate hands-on exposure to simulating HDLs. Finally, for the first time […]
In UVM, sequences can provide a wealth of functionality beyond initiating stimulus on a particular interface. Often designs require the verification environment to respond to traffic from the DUT, and sequences can model this behavior as well. By modeling responders through the use of Slave Sequences, UVM enhances reuse by encapsulating the functionality in sequences […]
Aldec delivers Rapid Debugging with UVM Toolbox™ to Interpret Complex UVM Verification Environments – 2014-08-05 – Newsroom – Company – Aldec
“Riviera-PRO already allows visualizing the testbench architecture and data flow between UVM components with its signature UVM Graph tool” said Satyam Jani, Riviera-PRO Product Manager, “UVM Toolbox extends Riviera-Pro’s debugging capabilities with easy-to-read, tree-like hierarchy that allows users to quickly locate components within a UVM verification environment.” UVM Toolbox displays object properties for components […]
This whitepaper discusses the semiconductor design challenges and how to automate the transition from specification to design for ASIC and FPGA projects. via 20 Advantages to Automate Specification to Design for ASICsAgnisys.