Aug
04
2015

IEEE invites contributions for the upcoming UVM (IEEE P1800.2) standard

IEEE, the world’s largest professional association for the advancement of technology is into action that directly impacts (in a positive way) all the Design-Verification community across the globe. In-line with IEEE’s constant endeavours to advancing the technology, it is now accepting a donation from Accellera, an electronics industry standards committee on UVM (Universal Verification Methodology) to […]

Dec
17
2014

Open Source VHDL Verification Methodology – OSVVM™ 2014.07a: Protected Types, Initialized Pointers, and Memory Leaks

Dec 16, 2014: OSVVM new release: As some of the VHDL users across the globe aware, OSVVM is an independent initiative by Jim Lewis of SynthWorks to promote VHDL based Verification. For those uninitiated, here is a quick start: http://cvcblr.com/?p=436 Open Source VHDL Verification Methodology announces release 2014.07a. As per the developer:  There are no new […]


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