Jun
29
2015

Benefits of native UVM VIP

Benefits of native UVM VIP     Srinivasan Venkataramanan, Chief Editor, http://www.VerifNews.org Shankar Hemmady Ever since the birth of Accellera UVM standard (and now on its way to becoming an IEEE 1800.2 standard), several companies have announced Verification Intellectual Properties (VIPs). The primary objective of UVM standardization committee was to develop a set of base […]

Jun
01
2015

Truechip announces CVIP for HDMI

May 27, 2015 – Truechip Solutions, the verification IP specialist, announced today that it has shipped early adopter version of its HDMI 2.0Comprehensive Verification IP (CVIP) to its partners in the early adoption program. This CVIP is natively developed in SystemVerilog (UVM) and is architected such that a single VIP is able to provide comprehensive, […]

May
01
2015

Truechip grows customer base, announces portable, comprehensive VIPs

One of the emerging VIP players from India, TrueChip (http://www.truechip.net)  was exhibiting at DVCon USA 2015 for the consecutive second year. Our VerifNews team caught up with Nitin Kishore, CEO of Truechip at their booth at the event.   Here is a transcript: VN: Tell us about your company please NK: Truechip is one of the first, built-from-scratch VIP […]

Jan
10
2015

Synopsys address Portable Stimulus through VC VIP Test Suites

The Verification Spectrum Typically, verification teams develop separate flows to support verification at block and SoC levels. As well as supporting reuse between these different abstraction levels, the verification environment should be reusable at different stages of the verification process, to minimize effort.   Figure 1: Two dimensions of the verification spectrum via SystemVerilog Test […]

Jan
10
2015

Mentor release its latest Issue of Verification Horizons

High quality quarterly newsletter from Mentor Graphics covering deep Functional Verification topics such as: Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide – Fast Track to Productivity Using Questa VIP -Takes you through a new set of productivity features that we’ve named“EZ-VIP” that provides predefined sequences,configuration objects and wrapper modules to function as […]

Dec
13
2014

Arrow Devices invites you for a quick survey on: What DV Topics Do You Care About In 2015?

At Arrow Devices, we pride ourselves in delivering products that truly solve your verification problems. In the same way, we strive to help you with content that helps you in solving design verification issues that you face everyday. What’s The Objective Of The Survey? To help us bring you even more compelling articles, technical comparisons […]

Nov
14
2014

Whiteboard Wednesdays—TripleCheck VIP – Cadence Community

In this week’s Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification IP (VIP) and how it allows engineers to know they have a thoroughly tested design that complies with the interface specification. via Whiteboard Wednesdays—TripleCheck VIP – Whiteboard Wednesdays – Cadence Blogs – Cadence Community.

Nov
11
2014

10 things to know about memory verification: Introducing Synopsys Memory VIP

On-demand webinar: Attendees Will Learn: Dynamic part selection; no need for re-compilation when selecting new part Intelligent, built-in JEDEC compliant Protocol and timing checks Pre-defined CoverGroups for Memory State transition, training and power down modes, and more Direct testbench access to the Memory Core for peek, poke, and set/get/clear any memory location attributes Error injections […]

Nov
08
2014

Mentor announces Lunch-n-learn event for MIPI CSI-2 and DSI Questa VIP

Date: Nov 17, 2014 12:00 PM – 1:00 PM US/Pacific Location: Fremont, CA – USA Register at: http://go.mentor.com/3ulv4 Mentor Graphics CSI-2 and DSI QVIP provides comprehensive protocol stimulus and coverage checking that allows you to easily deploy advanced verification methodologies. As well as a BFM and protocol checking assertions, our VIP includes testplans for Verification planning, constrained random […]

Nov
07
2014

Verifying ARM AMBA® 5 CHI Interconnect-Based SoCs Using Next-Generation VIP

To meet the low-power, performance and functionality demands of advanced electronics products, virtually every SoC designed today is a multicore SoC. In this environment, on-chip cache memory plays a critical role, as memory architecture is fundamental in determining system performance.Historically, CPU speed has outpaced memory speed. This performance gap led to the use of on-chip […]




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