Our next episode of DVTalk is here! Welcome to DVTalk April-2018. In this episode we are thrilled to partner with leading VLSI & EDA companies and standard committee to bring you the latest in this field. It is free to attend, but registration is mandatory. As seats gets filled quickly, we suggest you register right-away […]
Category: Webinar
Jan
15
2015
Aldec’s DO-254 Webinar Jan. 22: Validation and Verification Process for DO-254
Validation and Verification Process for DO-254 Date: Thursday, January 22, 2015 Register for India/EU 8.30 PM to 9.30 PM India time (4:00PM to 5:00PM CET) Register for US 11:00AM to 12:00PM PST (USA) Presenter: Randall Fulton, FAA Consultant DER Abstract: Requirements are central to the development process described in DO-254. The Validation and Verification Process ensures that requirements […]
Dec
16
2014
Aldec offers Joint Webinar Dec. 18: Best Practices for DO-254 Requirements Traceability w/ Richland Technologies
Best Practices for DO-254 Requirements Traceability Jointly Presented with Richland Technologies Date: Thursday, December 18, 2014 Register for EU 4:00PM to 5:00PM CET Register for US 11:00AM to 12:00PM PST Abstract: DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements […]
Nov
11
2014
Webinar: The Complete Solution for Register Specification, Design and Verification
Agnisys Webinar: The Complete Solution for Register Specification, Design and Verification When: Wednesday, November 12, 1:00 to 2:00 PM Eastern Standard Time Who should attend: Spec Writers, Architects, Designers, Verification Engineers, Firmware Developers What will you see: How to develop correct-by-construction register definitions from a single register specification Auto-generation of a range of outputs from a […]
Nov
11
2014
10 things to know about memory verification: Introducing Synopsys Memory VIP
On-demand webinar: Attendees Will Learn: Dynamic part selection; no need for re-compilation when selecting new part Intelligent, built-in JEDEC compliant Protocol and timing checks Pre-defined CoverGroups for Memory State transition, training and power down modes, and more Direct testbench access to the Memory Core for peek, poke, and set/get/clear any memory location attributes Error injections […]
Nov
11
2014
Synopsys announces webinar on Verdi’s VC Apps: Getting Started with Your First VC Apps
Schedule: Web event: Take Control of Your Flow: Getting Started with Your First VC Apps Date: November 11, 2014 Time:10:00 AM PST Duration: 45 minutes In this webinar we will: • Provide an introduction to the concepts and motivation for VC Apps • Walk through the available resources for VC Apps • Demonstrate how to use the VC Apps Toolbox included […]
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