Our next DVTalk event is scheduled for Oct 6th, Tuesday, 2015. The venue is Doubletree Hotel, Outer Ring Road, Bangalore. We have a great set of talks lined up, Click here for latest agenda: http://verifnews.org/2015/10/dvtalk-oct-6-agenda/


  • UVM 1.2 updates – Adithya Sharma, VerifLabs
  • How to Train your SystemVerilog Constraint? Jeremy Ridgeway, Avago, USA
  • Go2UVM – the fastest way to get started with UVM, Azhar, VerifLabs
  • UVM Rule checker, Vidhya, VerifWorks

It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basis. Please register herehttp://goo.gl/forms/84IVLZGzYi


How to Train your SystemVerilog Constraint – Jeremy Ridgeway

Jeremy_Ridgeway_Avago  SystemVerilog constraints are declarative–they must be elaborated prior to simulation. There is some flexibility at run-time when class members are used in the constraints or by enabling or disabling constraint blocks. Otherwise, to change the constraint, the containing class must be extended with a new or augmented constraint block, then instantiated in place of the original class, e.g. via the universal verification methodology (UVM) factory. Instead, we present a generic constraint container class that enables wholesale manipulation or replacement of the constraint on-the-fly via programming interface, or string based access in the UVM configuration database or directly on the simulation command-line. We have successfully employed this class at Avago Technologies in multiple projects over the last four years.

In this talk we will present the type-parameterized generic constraint container class, with the user-distribution constraint as our example ( dist { val := weight, … } ). We will discuss the programming interface and string parser front-ends, connections to the command-line and UVM configuration database, and the parameterized constraint factory that actually performs the instantiation. Then, we will evolve the container class to better mimic the conjunctive-normal form (CNF) formula that the simulator’s constraint solver actually solves. Finally, we suggest further enhancements and uses for the type-parameterized generic constraint container class.


Jeremy Ridgeway has sixteen years of computer hardware verification experience, specializing in serial protocols, such as PCI-Express and SAS (Serial Attached SCSI). He has worked at LSI Logic, Sierra Logic, and Emulex before all were purchased by Avago Technologies. Jeremy holds a Bachelor of Science in Computer Engineering from the University of Arizona, and a Masters of Science in Electrical Engineering from the University of Alabama. Prior to joining LSI/Avago in 2011, Jeremy was a PhD candidate researching Boolean Satisfiability at the University of Trento, in Trento, Italy.


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